36 results about "System on chip design" patented technology

A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Voltage islands enable a core-level power optimization of ASIC / SoC designs by utilizing a unique supply voltage for each cluster of the design. Creating voltage islands in a chip design for optimizing the overall power consumption consists of generating voltage island partitions, assigning voltage levels and floorplanning. The generation of voltage island partitions and the voltage level assignment are performed simultaneously in a floorplanning context due to the physical constraints involved. This leads to a floorplanning formulation that differs from the conventional floorplanning for ASIC designs. Such a formulation of a physically aware voltage island partitioning and method for performing simultaneous voltage island partitioning, level assignment and floorplanning are described, as are the definition and the solution of floorplanning for voltage island based designs executed under area, power, timing and physical constraints. The physical planning of voltage islands includes: a) characterizing cell clusters in terms of voltages and power consumption values; b) providing a set of cell clusters that belong to a single voltage island Random Logic Macro (RLM); and c) assigning voltages for the voltage island RLMs, all within the context of generating a physically realizable floorplan for the design.

A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. System on chip designs may employ a plurality of NOCs with different configuration parameters to customize the system to the application or workload characteristics. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM / HBM / HMC channels, PCI Express channels, and 10G / 25G / 40G / 100G / 400G networks.

A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improve the scan test coverage of the system-on-chip.

A data reading method for motion estimation in an embedded system is provided. The embedded system includes an external memory device and a video encoding device, wherein the external memory device stores a first frame, and the video encoding device has an internal memory. First, a second frame is divided into M×N sub frame sets, wherein each of the sub frame sets has O×P sub frames. Then, each of the sub frame sets is selected in a calculation sequence, and the selected sub frame set is stored into the internal memory. Next, a predicted search path of each sub frame in the selected sub frame set is calculated. Thereafter; a predicted reading range is determined, wherein the predicted reading range includes the predicted search paths of the sub frames. Finally, a comparison data is read from the first frame according to the predicted reading range.

The invention belongs to the field of on-chip system design and provides a system and a detection method for realizing low-voltage real-time detection of SoC chips. Among them, the register set inside the central processing unit includes a plurality of registers corresponding to different voltage levels of the VBAT voltage, and the processor of the on-chip power management module monitors the VBAT voltage stepwise according to the value of each register, and generates corresponding interrupt, the CPU will quickly respond to the low-power process according to the interrupt type. Through the setting of multiple VBAT voltage gears, multiple VBAT voltage gears can be monitored and warned at the same time, which enriches the low-voltage detection function and expands the application range.