Efficient interrupt system for system on chip design

Abstract

A method (400) and system (10) for managing interrupts in a system on a chip design that includes multiple processors (100a, 100b, ..., 100n) coupled to multiple peripheral devices (120a, 120b, ..., 120m). A plurality of interconnected interrupt controllers (110a, 110b, ..., 110n) are coupled between the processors and the peripheral devices. Interrupts generated by the peripheral devices are received by all of the interrupt controllers. In one embodiment, an interrupt controller is paired with a processor. Each interrupt controller can identify which interrupts will be passed to its respective processor. The interrupt controllers work in concert to pass each interrupt to a particular processor.

Description

technical field [0001] The present invention relates generally to the field of integrated circuits ("chips") and, more particularly, to implementing interrupt management in "system-on-chip designs" that include multiple processors and multiple peripherals. technical background [0002] "System-on-a-chip" architectures such as microcontrollers or microprocessors are commonly used in applications including audio, radio, portable devices, data communications, Internet control, and industrial and consumer systems. System-on-a-chip architectures provide design and manufacturing efficiencies in chip production and the integration of chips in specific applications. [0003] To improve performance, some system-on-chip architectures utilize multiple central processing units (CPUs). In addition, system-on-chip architectures may utilize multiple buses, typically arranged in some type of hierarchy. [0004] As the complexity of chips increases, some problems arise with system-on-chip ...

AI Technical Summary

Problems solved by technology

State-of-the-art interrupt management techniques may require complex and inefficient multi-bus designs

Additionally, existing techniques may not allow processors to communicate with each other regarding the handling of interrupt requests

In addition, the existing technology may assign certain interrupt requests to specific CPUs in the hardware, so the existing technology appears to be relatively fixed and inflexible

Moreover, existing technologies may force IC designers to face difficult timing and placement constraints, thereby significantly increasing the time to design and produce ICs

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