1687 results about "Switched capacitance" patented technology

The invention provides an optimal electric power converter for a DC / DC converter which variably steps up a voltage successively with an optional magnification of one to two times or more and / or step down a voltage successively with a step-down ratio of one time or less. The converter includes a first input-output part, an inductor connected with a positive or a negative electrode side of the first input-output part, plural switches, plural capacitors, a second input-output part connected with plural capacitors, and a control circuit, wherein the control circuit controls the plural switches with operation mode and makes the inductor and plural capacitors selectively functional, wherein the electric power converter is of a switched capacitance type that performs any operation out of step-up, step-down, regeneration, and continuity, and wherein the control circuit controls to have a period for which two switches out of the plural switches are simultaneously turned ON.

Capacitance measurement apparatus that enhances the sensitivity and accuracy of capacitive transducers, proximity sensors, and touchless switches. Each of two capacitors (C1, C2) under measurement has one end connected to ground and is kept at substantially the same voltage potential by operational amplifier (A1) or amplifiers (A0, A1) using negative feedback. The apparatus is driven by a periodic e.g. sinusoidal signal source (G1) or sources (G1, G2) and includes a difference amplifier (A2) operative to produce an electrical signal having a linear relationship with a specified arithmetic function of the capacitances of the two capacitors (C1, C2). A touchless switch is implemented using the capacitance measurement apparatus. The touchless switch includes two sensor electrodes (E1, E2) that correspond to the two capacitors (C1, C2) under measurement and in one embodiment has a front surface in the form of a container.

A plurality of thin-film capacitors are grouped in phases. A control circuit switches each phase between charging and discharging states devised to supply one or more loads with controlled power.

A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods. The charge from the sampling capacitors is averaged and transferred to the filter output during another non-overlapping time period.

The invention provides a voltage generating apparatus for powering at least one amplifier. The voltage generating apparatus comprises a voltage source, a switched capacitor voltage converter and a voltage detector. The voltage source supplies a first voltage to a positive voltage input terminal of the at least one amplifier. The first voltage is a positive DC voltage. The switched capacitor voltage converter is coupled to the voltage source for outputting an output voltage to a negative voltage input terminal of the at least one amplifier according to the first voltage and a predetermined voltage. The output voltage is a negative DC voltage. The voltage detector is coupled to the switched capacitor voltage converter for determining a switching frequency corresponding to the predetermined voltage according to the output voltage. The switched capacitor voltage converter increases the output voltage when the switching frequency is decreased and decreases the output voltage when the switching frequency is increased.

A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.

A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF / 2, 0, −C*VREF / 2 and −C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF / 2, A*VIN+0, A*VIN−VREF / 2 and A*VIN−VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A / D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

A charge pump method and apparatus is described having various aspects. Noise injection from a charge pump to other circuits may be reduced by limiting both positive and negative clock transition rates, as well as by limiting drive currents within clock generator driver circuits, and also by increasing a control node AC impedance of certain transfer capacitor coupling switches. A single-phase clock may be used to control as many as all active switches within a charge pump, and capacitive coupling may simplify biasing and timing for clock signals controlling transfer capacitor coupling switches. Any combination of such aspects of the method or apparatus may be employed to quiet and / or simplify charge pump designs over a wide range of charge pump architectures.

A method for constructing a direct-current to direct current (DC-DC) converter from an input voltage to an output voltage. The DC-DC converter has multiple capacitors and multiple switches connectible the capacitors. A target voltage ratio is obtained based on the input voltage and the output voltage. The target voltage is expressed as a radix number. The radix number is spawned into a code of the target voltage ratio. The code is translated into a switched-capacitor converter (SCC) configuration including the switches and the capacitors. The code may be an extended binary representation code or a Generic Fractional Numbers code. The switched-capacitor converter (SCC) configuration is preferably modified to obtain charge balance.