280results about "Switched capacitor networks" patented technology

A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

The present disclosure relates to a first active tunable low-noise RF bandpass filter that includes at least a first transistor element and a tunable frequency selective degeneration circuit coupled to a first non-inverting output of the first transistor element. The first active tunable low-noise RF bandpass filter combines low noise amplifier (LNA) and tunable bandpass filter functionalities into a single active RF bandpass filter. The tunable frequency selective degeneration circuit uses degeneration at frequencies outside of a passband of the active RF bandpass filter to increase feedback, thereby decreasing gain of the active RF bandpass filter. By decreasing the gain, linearity of the active RF bandpass filter may be improved in the presence of strong interfering RF signals, thereby enabling elimination of passive bandpass filter elements, such as surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, without degrading reception of in-band RF signals.

A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

A quadrature mixer with an LO input is provided. The quadrature mixer receives a signal having a frequency FLO and a signal input having a frequency FSIG, and has an output that comprises an output impedance that is high at frequencies of |FLO−FSIG | and |FLO+FSIG| and low at other. A mixer coupled to the output impedance interacts with the output impedance such that an impedance presented at the signal input is high for signals at FSIG if FSIG is a predetermined signal frequency, and low at other frequencies.

Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

A quadrature mixer with an LO input is provided. The quadrature mixer receives a signal having a frequency FLO and a signal input having a frequency FSIG, and has an output that comprises an output impedance that is high at frequencies of |FLO−FSIG | and |FLO+FSIG| and low at other. A mixer coupled to the output impedance interacts with the output impedance such that an impedance presented at the signal input is high for signals at FSIG if FSIG is a predetermined signal frequency, and low at other frequencies.

Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input / output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Methods and apparatus for sensing the output current in a switch mode power supply (SMPS) using primary side sensing are described. A module senses a current in a primary winding of a transformer and a voltage on a primary or auxiliary winding of the transformer, and which includes a multiplier coupled to an output of a signal averager averaging a primary winding current and to an output of a timing signal generator using the sensed voltage to signal when a secondary winding is powering an output of the SMPS, to multiply an averaged current sense signal by a fraction of a total cycle period of said SMPS during which the secondary winding is providing power to provide a signal estimating an output current of the SMPS.

A chopper-stabilized amplifier receiving an input signal includes a first operational transconductance amplifier having an input chopper and an output chopper for chopping an output signal produced by the first operational transconductance amplifier. A switched capacitor notch filter filters the chopped output signal by operating synchronously with the chopping frequency of output chopper to filter ripple voltages that otherwise would be produced by the output chopper. In one embodiment, a second operational transconductance amplifier amplifies the notch filter output. The input signal is fed forward, summed with the output of the second operational transconductance amplifier, and applied to the input of a fourth operational transconductance amplifier. Ripple noise and offset are substantially reduced.

A hybrid loop filter includes an integrator having an input and an output wherein the output forms an output of the hybrid loop filter, a plurality of transconductance amplifiers having an input and an output wherein each output of the plurality of transconductance amplifiers is coupled to the input of the integrator, a switched capacitor low pass chain having an input and a plurality of branches wherein each of the plurality of branches is coupled to the input of a separate one of said plurality of transconductance amplifiers, and a feedthrough branch having an input and an output wherein the input is coupled to the input of the switched capacitor low pass chain to form an input of said hybrid loop filter, and the output is coupled to the input of a separate one of the plurality of transconductance amplifiers.

A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors during multiple non-overlapping time periods. The charge from one set of sampling capacitors is averaged and transferred to the filter output during one non-overlapping time and the charge from another set of sampling capacitors is averaged and transferred to the filter output during a second non-overlapping time period.

A switched capacitor notch filter for sampling an input signal using multiple sampling capacitors and multiple non-overlapping time periods. The charge from the sampling capacitors is averaged and transferred to the filter output during another non-overlapping time period.

A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.

A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding half-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform.

Methods and apparatus for sensing the output current in a switch mode power supply (SMPS) using primary side sensing are described. A module senses a current in a primary winding of a transformer and a voltage on a primary or auxiliary winding of the transformer, and which includes a multiplier coupled to an output of a signal averager averaging a primary winding current and to an output of a timing signal generator using the sensed voltage to signal when a secondary winding is powering an output of the SMPS, to multiply an averaged current sense signal by a fraction of a total cycle period of said SMPS during which the secondary winding is providing power to provide a signal estimating an output current of the SMPS.

A low-pass filter configured as a switched capacitor circuit in which capacitor charge switching is performed by 2-phase clock signals that control respective sets of switching elements, wherein an interval between a first-phase clock signal pulse and a succeeding second-phase clock signal pulse, during which no charging / discharging of capacitors should occur, is made as short as possible while ensuring that the two sets of switching elements cannot enter the ON state simultaneously. A low cut-off frequency can thereby be achieved, while using very small capacitor values.

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.

There is provided a charge domain filter device including a plurality of transconductors each of which converts an input voltage to a current and outputs the current and a filter unit that filters output signals from said plurality of transconductors by repeatedly charging and discharging a plurality of capacitors, wherein an impulse response of the charge domain filter device is obtained through convolution of a first impulse corresponding to a charge time length over which said capacitors are charged and a second impulse corresponding to each of said plurality of transconductors.

A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated / deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.

There is provided a signal generating apparatus including: a multiphase oscillating portion for generating a number of base signals having the same frequency and a predetermined phase difference of which the signal level transitions between a first level and a second level, and where periods during which the signal level of any given base signal is at the first level and the signal level of the next base signal having the predetermined phase delay relative to the given base signal is at the first level overlap; and a transition time point changing portion for generating a pulse signal by changing the time point when each base signal transitions from the first level to the second level to a time point before the next base signal transitions from the second level to the first level.

According to the present invention, a switched capacitor circuit comprises: an inverting amplifier for removing the offset by using a chopper stabilization circuit; a sampling unit which is connected between an input terminal and the inverting amplifier; and a feedback unit which is connected to the inverting amplifier in parallel.

A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.