Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

623 results about "Non critical" patented technology

Method and apparatus for deterministic replay of java multithreaded programs on multiprocessors

A method (and apparatus) of determinstically replaying an observable run-time behavior of distributed multi-threaded programs on multiprocessors in a shared-memory multiprocessor environment, wherein a run-time behavior of the programs includes sequences of events, each sequence being associated with one of a plurality of execution threads, includes identifying an execution order of critical events of the program, wherein the program includes critical events and non-critical events, generating groups of critical events of the program, generating, for each given execution thread, a logical thread schedule that identifies a sequence of the groups associated with the given execution thread, and storing the logical thread schedule for subsequent reuse.
Owner:IBM CORP

Flexible cable for high-speed interconnect

A system and method are disclosed in which flex cables are affixed to PCBs, for providing high-speed signaling paths between ICs disposed upon the PCBs. The flex cables are fixably attached to the PCBs so as to substantially mimic their structural orientation. Where the configuration includes more than one PCB, the flex cables include multiple portions which are temporarily separable from one another and from the die, using flex-to-flex and flex-to-package connectors, allowing field maintenance of the configuration. By routing the high-speed signals between ICs onto the flex cable, single-layer PCBs can be used for non-critical and power delivery signals, at substantial cost savings. By disposing the flex cables onto the PCB rather than allowing the cables to float freely, the configuration is thermally managed as if the signals were on the PCB and cable routing problems are avoided.
Owner:INTEL CORP

Method, program product and apparatus for performing double exposure lithography

A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process. The method includes the steps of: defining an initial H-mask corresponding to the target pattern; defining an initial V-mask corresponding to the target pattern; identifying horizontal critical features in the H-mask having a width which is less than a predetermined critical width; identifying vertical critical features in the V-mask having a width which is less than a predetermined critical width; assigning a first phase shift and a first percentage transmission to the horizontal critical features, which are to be formed in the H-mask; and assigning a second phase shift and a second percentage transmission to the vertical critical features, which are to be formed in the V-mask. The method further includes the step of assigning chrome to all non-critical features in the H-mask and the V-mask. The non-critical features are those features having a width which is greater than or equal to the predetermined critical width. The non-critical features are formed in the H-mask and the V-mask utilizing chrome. The target pattern is then imaged on the substrate by imaging both the H-mask and V-mask.
Owner:ASML NETHERLANDS BV

Smartly formatted print in toolbar

The subject invention provides for systems and methods that allow a web user to more easily and readily print what they actually want to print and at the same time, mitigates user frustration that often ensues from poor web page printing. More specifically, the subject invention involves deciphering a structure or layout of any web page on the Internet. When a user employs the present print feature, the invention can be invoked to analyze the structure of a current web page to automatically generate a print preview page of the current web page. After analyzing the current web page, extraneous content of the page that is deemed to be non-critical or non-essential to that web page can be removed for printing purposes. Furthermore, previous knowledge learned regarding web page structure can be applied to determine the page and / or content structure of the current page to facilitate generating the print preview page.
Owner:MICROSOFT TECH LICENSING LLC

Hardware/software based indirect time stamping methodology for proactive hardware/software event detection and control

An improved method and apparatus for time stamping events occurring on a large scale distributed network uses a local counter associated with each processor of the distributed network. Each counter resets at the same time globally so that all events are recorded with respect to a particular time. The counter is stopped when a critical event is detected. The events are masked or filtered in an online or offline fashion to eliminate non-critical events from triggering a collection by the system monitor or service / host processor. The masking can be done dynamically through the use of an event history logger. The central system may poll the remote processor periodically to receive the accurate counter value from the local counter and device control register. Remedial action can be taken when conditional probability calculations performed on the historical information indicate that a critical event is about to occur.
Owner:IBM CORP

Routing shipments according to criticality

A computer-implemented method for routing shipments according to criticality includes accessing an initial solution to an optimization problem of routing multiple shipments to multiple locations using multiple vehicles, the initial solution including multiple loads such that each shipment is routed within exactly one load and a global cost across all loads is minimized, the initial solution being generated independent of the criticality of the shipments. Into each of one or more critical loads in a current solution, one or more non-critical shipments are inserted that are within a neighborhood of the critical load, a critical load being a load containing at least one critical shipment. One or more local search operations are executed to improve the initial solution, the operations including at least one of: (a) splitting each of one or more selected critical loads in a current solution into two new critical loads; (b) for each of one or more selected critical load pairs in a current solution, move a sequence of stops from one critical load in the pair to the other critical load in the pair and / or swap two sequences of stops between the critical loads in the pair; and (c) for each of one or more selected critical loads in a current solution that are indirect critical loads having at least one in-transit stop, break up the indirect critical load into a plurality of new direct critical loads having no in-transit stops and execute operation (b) on each of one or more selected critical load pairs, each selected critical load pair including at least one new direct critical load.
Owner:BLUE YONDER GRP INC

Method for high-efficiency task scheduling of heterogeneous multi-core processor

InactiveCN102193826ARaise priorityOptimize calculation resultsEnergy efficient ICTResource allocationEarliest finish timeCritical path method
The invention provides a method for high-efficiency task scheduling of a heterogeneous multi-core processor. The method comprises the following steps of: clustering certain special tasks which are large in communication overhead and easy to cluster in a task image to a precursor node of the tasks by adopting a linear task clustering method; starting from a topological structure of the whole task image, selecting parameters capable of comprehensively reflecting the importance of the task in the whole task image as priority weights; selecting a free critical path node to perform allocation first, and if multiple free critical path nodes exist, allocating the free critical path nodes in a sequence from high to low according to the node priority weights, and allocating all non-critical path free nodes in a sequence from high to low according to the priority weights; performing redundancy judgment, and deleting redundant tasks in a scheduling result; and performing adjustment according to the scheduling result after deleting the redundant tasks, and recalculating the earliest finish time of each task. According to the method, the efficiency of the task scheduling of the heterogeneous multi-core processor is improved, the power consumption of the processor is reduced, and the performance of the multi-core processor is promoted.
Owner:HARBIN ENG UNIV

System and user interface for configuring and presenting a trend indicative display of patient medical parameters

A system provides an electronic patient parameter Flowsheet offering the flexible features of a paper chart by enabling user configurability of a Flowsheet trend indicative display to incorporate and locate desired patient parameters and associated data items and properties and to hide non-critical supplementary data. A system configures a user interface presenting patient medical parameter data in a trend indicative display indicating a time period comprising user selectable acquisition time intervals. An acquisition processor acquires, from a patient monitoring device, data representing a patient parameter. A processor initiates generation of data representing at least one display image for use in configuring a trend indicative display of a patient parameter and an associated data item by enabling user selection of the data item for trend indicative display and by enabling user association of the data item with a property indicating at least one of, (a) the data item represents volume data to be used in patient fluid infusion or output calculation, (b) the data item represents a rate for use in calculation of volume of patient fluid infusion or output and (c) the data item value is to be used in multiple acquisition time intervals of the trend indicative display.
Owner:DRAGERWERK AG

Method and Apparatus for Extracting Systematic Defects

The present disclosure provides a method of systematic defect extraction. Primary and secondary areas are defined in a wafer layout. A plurality of defects is identified by a first wafer inspection for an outside-process-window wafer. Defects located in the secondary area are removed. Defects associated with non-critical semiconductor features are also removed via a grouping process. Sensitive regions are defined around defects associated with critical semiconductor features. A second inspection is then performed on the sensitive regions for an inside-process-window wafer, thereby identifying a plurality of potentially systematic defects. Thereafter, a Scanning Electron Microscopy (SEM) process is performed to determine whether the defects in the sensitive regions of the inside-process-window wafer are true systematic defects.
Owner:TAIWAN SEMICON MFG CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products