51 results about "Cross bar switch" patented technology

A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.

The invention relates to a precise resistance measuring device. One end of a resistor to be measured is connected to the anode of a power supply through a reference resistor and a current-limiting resistor, and the other end is grounded through a bias resistor; four input ends of a cross bar switch are respectively connected to two ends of the reference resistor and the resistor to be measured, and two output ends of the cross bar switch are respectively connected to the same-phase input end and the reverse-phase input end of a signal amplification circuit; the signal amplification circuit is connected to the data signal input end of a central processor through an A / D converter; the data signal output end of the central processor is connected with a memory; the control signal output end of the central processor is connected with the control signal input end of the cross bar switch to control the two output ends of the cross bar switch to sequentially output positive and negative voltage of two ends of the reference resistor and positive and negative voltage of two ends of the resistor to be measured; the positive and negative voltage of two ends of the reference resistor and the resistor to be measured is stored in the memory by the central processor through the processing by the signal amplification circuit and the A / D conversion by the A / D converter; and the central processor transfers the positive and negative voltage difference of the reference resistor and the positive and negative voltage difference of the resistor to be measured and carries out calculation to obtain the resistance value of the resistor to be measured.

Embodiments of the present invention provide a system and method for providing non-blocking routing of optical data through an optical switch fabric. The optical switch fabric can include an optical switching matrix with a plurality of inputs intersecting with a plurality of outputs. A path switch can be located at each intersection that is operable to switch data arriving on an input to a particular output. The path switches can be configurable to create a plurality of unique paths through the optical switching matrix to allow routing in a non-blocking manner. Another aspect of the present invention can provide a system and method for providing non-blocking routing through an optical cross-bar switch. The optical cross-bar switch includes a plurality of input links, a plurality of output links and a plurality of switching elements. Each switching element can include a plurality of path switches connecting each of the input links to at least one of the output links and the plurality of switching elements can be configured to create a plurality of unique paths through the optical cross-bar switch.

A multi-processor system on chip (SoC) platform and a DVB-T baseband receiver using the same are disclosed. The multi-processor SoC platform includes a first processor, at least one second processor, at least one slave device communicating with the first processor and the second processor and a communication interface (CI) unit connecting the slave device to the first processor and the second processor according to a cross-bar switching method to allow the slave device to be communicated with the first processor and the second processor. Therefore, the multi-processor SoC platform having flexibility with being adapted for high speed calculation by using a cross-bar switch is provided.

Low speed switches operated under the common control of a global scheduler can be used to switch high speed data while preserving packet ordering if the incoming packets are queued in a temporal order. By operating several low speed switches in parallel, a high-speed switching capacity can be realized.

A link module architecture is disclosed for use with a multi-core central processing unit having a cross bar switch. The link module comprises timing recovery circuitry operably coupled to the central processing unit, wherein the timing recovery circuitry is positioned proximate to the cross bar switch. The link module further comprises a bit receiver operably coupled to the central processing unit, and a bit output driver operably coupled to the central processing unit. The bit receiver, preferably comprising a wide bandwidth amplifier, and the bit driver are preferably integrated with a sea of on-chip RAM.