89 results about "Buffer design" patented technology

The invention provides an apparatus and method for realizing an accelerator of a sparse convolutional neural network. According to the invention, the apparatus herein includes a convolutional and pooling unit, a full connection unit and a control unit. The method includes the following steps: on the basis of control information, reading convolutional parameter information, and input data and intermediate computing data, and reading full connected layer weight matrix position information, in accordance with the convolutional parameter information, conducting convolution and pooling on the input data with first iteration times, then on the basis of the full connected layer weight matrix position information, conducting full connection computing with second iteration times. Each input data is divided into a plurality of sub-blocks, and the convolutional and pooling unit and the full connection unit separately operate on the plurality of sub-blocks in parallel. According to the invention, the apparatus herein uses a specific circuit, supports a full connected layer sparse convolutional neural network, uses parallel ping-pang buffer design and assembly line design, effectively balances I / O broadband and computing efficiency, and acquires better performance power consumption ratio.

A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input / output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.

The invention discloses a design method of an arithmetic coder, and a realization device, which comprise a front-buffer design, algorithm structure joint optimization, a muti-bin processing technology and a hybrid context storage mechanism, wherein the front-buffer design is used for solving the problems that the number of binary sequences (bin) generated by a macroblock after binary conversion can fluctuate within a very wide range, but the number of the binary sequences (bin) processed by a binary arithmetic coding module (BAC) in unit time is limited; the algorithm structure joint optimization mainly uses a time borrowing technology to place low processing after range processing; the muti-bin processing technology utilizes MPS (microprocessor system) computation more easily compared with an LPS (lean process solution), so that people can process multiple MPSs in a clock period; and the hybrid context storage mechanism is a storage method invented for a special application of a 2bins / cycle throughput rate, can store a large number of context models, and can conduct quick memory on the models. The arithmetic coder and the coding method are applicable to coding of a multi-stage pipeline structure, in particular to real-time coding of high-definition resolution.

The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online / offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

A buffer design for an integrated circuit that not only recognizes, but improves upon the skew problem as described above that is particularly problematic in cases where the output buffer supply voltage is particularly close or the same as the voltage of the signals coming from the core of an IC. Translator-up circuits associated with output buffers are implemented in parallel with respective selective bypass circuits, allowing the translator-up circuit to be inserted into or removed from a signal path based on the voltage level of a signal received from the inner core and the voltage level required by the output buffer. When the voltage level of the “higher” voltage side is equal to the “lower” voltage signal level, the translator-up circuits are bypassed through selection by a selective bypass circuit. Thus, a selective bypass circuit is implemented together with a translator-up circuit to eliminate large signal skew, and to generally speed up circuit performance.

A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input / output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

A hammering tool with buffer design includes: a hammering member, a protrusion block section extending from a lower side of the hammering member, a right side of upper section of the protrusion block section being notched to form a first receiving space; a handle member having a grip section, a first plate section, a second plate section and a third plate section being disposed at an upper end of the grip section to define a receiving chamber for inserting the protrusion block section therein; a pivot member for pivotally connecting the protrusion block section of the hammering member with the handle member; and a buffer assembly including a first compression spring received in the first receiving space. A right end face of the protrusion block section of the hammering member is spaced from a left face of the first plate section by a predetermined buffering distance.

The invention relates to a binning device, in particular to a binning device used after tobacco leaf sorting. In order to solve the problem of excessive cylinder stroke and loud sound of the binning mechanism in the existing tobacco leaf binning device, the invention provides the binning device used after the tobacco leaf sorting. The binning device comprises a power mechanism and at least one binning station; the binning station comprises a transmission mechanism, a conveying mechanism and a binning mechanism, wherein the power mechanism drives the transmission mechanism to move, the transmission mechanism and the conveying mechanism are in a co-movement relation, and the binning mechanism performs the binning process on tobacco leaves transported by the conveying mechanism. By adopting the binning device, the cylinder movement stroke is reduced, and the speed of the binning is improved, so that the 10 pieces / s production capacity requirement of equipment is satisfied; a limiting buffer design can effectively reduce the impact and reduce the noise of the impact when binning; whole screws are fixed by adopting an anti-loose design, thereby meeting the frequent movement of the mechanism; and the binning device also has the characteristics of durability, stability and firmness.