104results about How to "Sufficient margin" patented technology

Cassette (50) performs assays, e.g. multiplexed protein biomarker assays. Wide, bubble-free, slow flows are produced from liquids stored on cassette (50), flowing over wide array (20) of ligand receptors on a capture surface. Flows of Reynolds Number less than about 1, preferably 1×10−1 to 5×10−3, are heated in region (34) preceding and including bubble removal system (128). Analyte is introduced through compressed septum (32). External actuations of displacement pumps (30, 37) and valves (137 A, B, and C) produce flows in response to flow-front optical sensors (150, 152). Elastic sheet provides pump and valve diaphragms and resilient expansion of mixing volume (131). Break-away cover portions are pistons. Heating is by conduction through cassette from external contact heater. Planar cassette body, when tilted from horizontal, enables upward flow from pumped storage (134, 135) to reaction (133) to waste (139), with buoyancy bubble removal before reaction. Reading of fluorescence is by external reader, employing calibration, control and reference features on capture surface. Extensive set of calibration features of differing intensities enables self-calibration.

A communication cable is provided that satisfies the requirement of Cat.6 for near-end cross talk wherein the difference between the maximum and minimum values of delay time among the four twisted wire pairs constituting the cable is within 25 ns / 100 m. The communication cable is made by entwining four twisted wire pairs (T1), (T2), (T3), (T4) made by twisting pairs of insulated wires made by covering electrically conductive wires by polyolefin thermoplastic resin with each pair being twisted with a twist pitch different from the others (pitch: P1<P2<P3<P4) and the inter-pair interposer (6) made of polyolefin thermoplastic resin, while being entwined with each wire pair, around a central interposer (2) made of polyolefin thermoplastic resin having cross sectional area of S1. Cross sectional area S1 of the central interposer (2) satisfies the relationship of inequality S1>=[{4.1 d / (1+{square root over (2)})}.0.35]2xpi, while the inter-pair interposer (6) that is entwined with the twisted wire pairs is located at such a position as adjoins the twisted wire pair (T1) having the least pitch P1 and does not adjoin the twisted wire pair (T4) having the largest pitch P4.

A hybrid electric vehicle 1 has a battery state detecting unit for detecting a temperature and SOC of a battery pack, a storage unit for storing a first target SOC calculation map in which a battery temperature and a target SOC which enables regenerative power generation at that battery temperature are associated with each other, and a second target SOC calculation map in which a battery temperature and a target SOC which enables startup of an internal combustion engine at that battery temperature are associated with each other, and a charging / discharging control unit for acquiring a target SOC which corresponds to the detected battery temperature based on the first target SOC calculation map or the second target SOC calculation map to control charging / discharging so that the detected SOC matches the acquired target SOC.

A display substrate includes gate lines, driving circuit part, signal lines, connection lines and a contact part. Gate lines are formed on a display area and intersect data lines. Driving circuit part is formed on a peripheral area surrounding the display area and provides a gate signal to the gate lines. Signal lines are formed adjacent to the driving circuit part and provide a driving signal to the driving circuit part. Connection lines include a first end portion overlapped the signal lines and a second end portion electrically connected with the driving circuit part. A contact part is formed on the signal lines and connects the first end portion with the signal lines.

A controller for a vehicle including at least one motor driving wheels, an inverter driving the motor, and a boosting converter supplying a dc power supply current to the inverter, is provided with a control portion performing rectangular wave control and non-rectangular wave control on the inverter in a switched manner. The control portion has an emergency switching condition for switching control from the rectangular wave control to the non-rectangular wave control, as a determination reference, and when the emergency switching condition is satisfied while the rectangular wave control is being executed (YES at step S5), the control portion instructs the boosting converter to lower target output voltage (S7). Preferably, the control portion determines that the emergency switching condition is satisfied when a q-axis current supplied from the inverter to the motor exceeds a prescribed threshold value.

The invention relates to a method for generating free gaits for a four-footed bionic robot. All of the free gaits of the four-footed robot are programmed according to moving periods, and each moving period comprises a four-footed supporting stage and a stepping stage; at the four-footed supporting stages, four feet of the robot are all positioned at supporting phases, the center of gravity of the robot moves in the advancing direction and the side directions of the advancing direction, in the advancing direction, the robot moves the largest advancing distance allowed by a current state, and in the side directions, the moving distance of the robot is determined taking account of the stability and the energy consumption of the robot at the same time; at the stepping stages, one foot of the robot is positioned at a swinging phase, and the other three feet of the robot are positioned at the supporting phases; when the swing foot of the robot for a certain moving period comes in contact with the ground, the movement of the robot for the next moving period is programmed. Through the adoption of the method, the adaptability of the four-footed robot to terrain is effectively improved, the stability of the robot can be improved, the continuity of the movement of the robot is ensured, the energy consumption is reduced, and the mean movement speed is accelerated.

A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

A wind energy installation includes a wind rotor, a double-fed asynchronous generator driven by the wind rotor, a converter provided with a first part on the generator side connected to a rotor and a second part on the network side connected to a stator of the generator, and a control device providing converter regulation. A mode selector can be switched between a normal operating mode and a reduced voltage operating mode, in which the excitation of the generator is reduced compared to the normal operating mode. The under-excitation produces an additional reactive current, thus reducing the rotor voltage. The rotor voltage can be limited even when the load is high and the network frequency or voltage is incorrect. The usable rotation speed range of the wind energy installation can be extended to provide a more powerful generator with a higher rating, without changing the converter.

Method for generating a flight speed profile of an aircraft (100) according to an RTA constraint, characterized in that it permanently calculates, at any point of the flight plan, a speed setpoint VΩ(X) of the aircraft determined on the basis of reference speed profiles, comprising at least a minimum speed profile Vmin(X), and a maximum speed profile Vmax(X). The method can also take into account an optimum speed profile Vopt(X) determined, for example, on the basis of a cost or performance index.

Method for generating a flight speed profile of an aircraft (100) according to an RTA constraint, characterized in that it permanently calculates, at any point of the flight plan, a speed setpoint VΩ(X) of the aircraft determined on the basis of reference speed profiles, comprising at least a minimum speed profile Vmin(X), and a maximum speed profile Vmax(X). The method can also take into account an optimum speed profile Vopt(X) determined, for example, on the basis of a cost or performance index.

A method and apparatus for controlling handover between a first technology network and a second technology network by detecting information about regions of an area of the first technology network, and deciding whether to initiate a handover procedure between the first and second technology networks based on the detected region information.

An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.

A valve timing control apparatus includes a driving-side rotary body, a driven-side rotary body, a fluid pressure chamber partitioned into a retard angle chamber and an advance angle chamber by a partitioning portion provided in at least one of the driving-side rotary body and the driven-side rotary body, a fluid control mechanism for controlling feeding of working fluid from a working fluid pump for feeding the working fluid to the fluid pressure chamber and controlling also discharging of the working fluid from the fluid pressure chamber, a first lock mechanism capable of restraining a relative rotational phase to a first predetermined phase between a most retarded angle phase and a most advanced angle phase, and a second lock mechanism capable of restraining the relative rotational phase to a second predetermined phase different from the first predetermined phase.

A firearm cartridge with a rimmed metal case having a body portion having a rim and a cylindrical wall portion adjacent to the rim. The body portion has dimensions corresponding to a 22 Long Rifle specification. The case has a tapered shoulder portion contiguous with the first portion, and a neck portion contiguous with the shoulder portion and a defining a mouth. The mouth closely receives a bullet having a diameter less than .22 caliber, and the case has a length significantly greater than 0.66 inch. The case may be formed with a neck that is relatively short compared to the body portion and overall length, to provide improved cartridge trajectory performance.

Reading methods of a nonvolatile semiconductor memory device are described herein. Methods may include supplying, to a word line, one of a voltage corresponding to a highest reading level or a voltage having a level higher than a first reading level of a read operation to be performed on the word line, and subsequently supplying a voltage of the first reading level to the word line and performing the read operation.

An object is to provide a semiconductor memory device which can be miniaturized and also secures a sufficient margin for the refresh period. A memory cell includes a reading transistor, a writing transistor, and a capacitor. In the above structure, the capacitor controls a potential applied to a gate of the reading transistor. The writing transistor controls writing and erasing of data and, when the transistor is off, has small current so that loss of electric charges stored in the capacitor, which is due to leakage current of the writing transistor, can be prevented. A semiconductor layer included in the writing transistor is provided so as to extend from the gate electrode toward a source region of the reading transistor. The capacitor is provided to overlap with the gate electrode of the reading transistor.

Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data strobe signal to an outside of a semiconductor device so as to indicate synchronization between an external device and data input / output; and a preamble part for maintaining an output of the strobe output driver to a predetermined logic level during a predetermined delay time from an enabling timing of the preamble signal. Accordingly, it is possible to guarantee the stable operation of the semiconductor memory even when PVT (processor, operating voltage, operating temperature) changes.

The invention discloses 700 MPa-grade hot-rolled container steel and a low-cost production method thereof. The hot-rolled container steel has corrosion resistance, cold bending property, and of the container steel comprises the following alloy composition of, in percentage by mass, 0.05-0.09% of C, 1.20-1.50% of Mn, 0.35-0.50% of Si, 0.020-0.050% of Al, 0.20-0.40% of Cu, 0.50-0.70% of Cr, 0.070-0.100% of Ti, not greater than 0.015% of P, not greater than 0.005% of S, not greater than 0.0060% of N and not greater than 0.005% of O. According to the 700 MPa-grade hot-rolled container steel and the low-cost production method thereof, the hot-rolled container steel component design is low in alloy content, pure in molten steel, and capable of saving the cost on the basis of ensuring excellent performance; and the high compression ratio is achieved, and the structure and the performance of finished products are improved; and in terms of mechanical property, various indexes meet the requirements, and the surplus amount is relatively sufficient.

In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode; and a longitudinal insulated gate static induction transistor in which the other side of the silicon pillar is used as an active region (a source region, a channel formation region and a drain region), and a bit line is connected to the silicon pillar.

A wind energy installation includes a wind rotor, a double-fed asynchronous generator driven by the wind rotor, a converter provided with a first part on the generator side connected to a rotor and a second part on the network side connected to a stator of the generator, and a control device providing converter regulation. A mode selector can be switched between a normal operating mode and a reduced voltage operating mode, in which the excitation of the generator is reduced compared to the normal operating mode. The under-excitation produces an additional reactive current, thus reducing the rotor voltage. The rotor voltage can be limited even when the load is high and the network frequency or voltage is incorrect. The usable rotation speed range of the wind energy installation can be extended to provide a more powerful generator with a higher rating, without changing the converter.

An apparatus for driving light emitting elements includes a constant-current driver arranged for each of arrays of light emitting elements including a constant-current drive element and a current regulator; a first selector configured to select one having a highest signal level from among control signals of the constant-current drivers and output the selected control signal; a second selector configured to select a lowest one from among output voltages of the constant-current drivers and output a signal representative of the selected output voltage; a differential amplifier configured to output an amplified differential signal that is obtained by amplifying a difference between the signals output from the first and second selectors; and a power source circuit configured to control, according to the amplified differential signal, a voltage supplied to a second end of each of the arrays of light emitting elements.

An organic light emitting diode device includes a gate electrode of a first transistor on a substrate; a gate insulation film on the gate electrode of the first transistor; a source electrode of a second transistor on the gate insulation film and overlapping with the gate electrode of the first transistor; a contact hole exposing the gate electrode of the first transistor and the source electrode of the second transistor; a conductive wiring in the contact hole, for electrically connecting the gate electrode of the first transistor and the source electrode of the second transistor.

Reading methods of a nonvolatile semiconductor memory device are described herein. Methods may include supplying, to a word line, one of a voltage corresponding to a highest reading level or a voltage having a level higher than a first reading level of a read operation to be performed on the word line, and subsequently supplying a voltage of the first reading level to the word line and performing the read operation.

A power generation plant comprising a power generating unit that includes at least one first generator, such as an induction generator, coupled to at least one synchronous generator having a rotor with a superconducting (SC) coil. The induction generator and the SC synchronous generator are coupled so that the SC synchronous generator supplies the induction generator with reactive power. Sufficient reactive power is preferably generated by the SC synchronous generator to meet the demand of the induction generator for VARs, as well as permit the induction generator to have a relatively large airgap.

Emergence of fretting worn powder is to be suppressed, and intrusion of the worn powder that has emerged into an internal area of the bearing. A ring spacer is interposed between an end face of an inner ring of the bearing to be mounted on a wheel axle, and an end face of a rear cover (ring member) to be mounted on the wheel axle for axial positioning of the inner race with respect to the wheel axle. An elastic seal ring is integrally fixed to an outer periphery of the ring spacer. The elastic seal ring is elastically fitted to an outer circumference of a recessed stepped portion formed on the end face of the rear cover. The elastic seal ring is thus pressed against the opposing end faces of the inner race and the rear cover. Inside the elastic seal ring, a storage space for the worn powder is provided.

Provided is a data strobe signal generating circuit capable of guaranteeing a preamble time (tRPRE). The data strobe signal generating circuit includes: a strobe output driver for outputting a data strobe signal to an outside of a semiconductor device so as to indicate synchronization between an external device and data input / output; and a preamble part for maintaining an output of the strobe output driver to a predetermined logic level during a predetermined delay time from an enabling timing of the preamble signal. Accordingly, it is possible to guarantee the stable operation of the semiconductor memory even when PVT (processor, operating voltage, operating temperature) changes.

A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.