30results about How to "Reduce the probability of flipping" patented technology

The invention relates to a well isolation type anti-SEU multi-node overturning storage unit layout structure. The well isolation type anti-SEU multi-node overturning storage unit layout structure comprises well isolation areas (201), (202), (203), DICE unit areas (101), (103), (105), (107) and DICE units (102), (104), (106), (108). The well isolation areas are arranged between two DICE unit areas in a crossed manner. According to the well isolation type anti-SEU multi-node overturning storage unit layout structure, compared with the prior art, the distance between sensitive node pairs is further increased while all the sensitive node pairs in a DICE storage unit structure are effectively separated; and the well isolation structure is also beneficial for reducing the parasitic bipolar transistor effect and charge sharing effect between the sensitive node pairs, so that multi-node overturning caused by SEU in the DICE units is greatly inhibited, and the anti-SEU performance of anti-radiation SRAM is greatly improved.

The invention discloses a register circuit for preventing a single particle from being overturned. The register circuit comprises a first-grade main latch, a second-grade secondary latch, a first inverter and a second inverter. The first-grade main latch is provided with two data inputs which are respectively selected form a data input di of a register and a complementary data input dib of the register; the first-grade main latch is provided with one clock input ck; the first-grade main latch is provided with two data outputs which respectively comprise latching data ql and complementary latching data qlb; the second-grade secondary latch is provided with two data inputs which are respectively selected form a data output ql and a complementary data output qlb of the first-grade main latch; the second-grade secondary latch is provided with one clock input ck and is selected from a complementary clock input ckn of the register; and the second-grade secondary latch is provided with two data outputs which respectively comprise registering data rq and complementary registering data rqb of the register. With the adoption of the register circuit disclosed by the invention, the anti-radiation performance of the register is obviously enhanced.

The invention discloses an encoding and decoding circuit based on low power consumption combination applied to a network on chip and an encoding and decoding method thereof. The encoding and decoding circuit is characterized in that an encoding circuit is arranged at the input end of a source node, and a decoding circuit is arranged at the output end of a destination node; the encoding circuit comprises an encoding judgment splitting module, four Hamming distance calculating modules, four data turning modules, a gray code encoding module, and a data encoding packaging module; and the decoding circuit comprises a decoding judgment splitting module, four data anti-turning modules, a gray code decoding module, and a data decoding packaging module. The turning rate of transmitted data can be reduced, so that the power consumption of the whole network on chip is reduced, and correct data transmission is ensured.

Provided is a semiconductor circuit device in which soft error resistance is enhanced while assuring the high-speed operation of an entire LSI circuit. A CAD device includes: means for identifying a signal transmission time of each signal transmission circuit of the LSI circuit; means for identifying an output inversion ratio upon radiation exposure of a flip-flop circuit of each signal transmission circuit; means for identifying a signal transmission circuit as a critical path; means for calculating a soft error ratio of the entire LSI circuit according to the signal transmission time, the output inversion ratio, and the clock cycle; and means for lowing the soft error ratio of the entire LSI circuit without changing the signal transmission time of the signal transmission circuit as the critical path when a predetermined soft error ratio is lower than the soft error ratio of the entire LSI circuit.

The invention discloses an encoding and decoding circuit based on low power consumption combination applied to a network on chip and an encoding and decoding method thereof. The encoding and decoding circuit is characterized in that an encoding circuit is arranged at the input end of a source node, and a decoding circuit is arranged at the output end of a destination node; the encoding circuit comprises an encoding judgment splitting module, four Hamming distance calculating modules, four data turning modules, a gray code encoding module, and a data encoding packaging module; and the decoding circuit comprises a decoding judgment splitting module, four data anti-turning modules, a gray code decoding module, and a data decoding packaging module. The turning rate of transmitted data can be reduced, so that the power consumption of the whole network on chip is reduced, and correct data transmission is ensured.

Disclosed is a parallel scrambling method for preventing single event upset in space. The method comprises the steps of creating a first scrambling code table, a second scrambling code table and a third scrambling code table in an FPGA; adopting an 8-level shift register to dynamically generate a scrambling code sequence according to scrambling polynomial; writing the generated scrambling code sequence into the same addresses of the first scrambling code table, the second scrambling code table and the third scrambling code table according to bytes at the same time; reading formatted data, reading a first scrambling code from the first scrambling code table, reading a second scrambling code from the second scrambling table and reading a third scrambling code from the third scrambling code table at the same time, and conducting two-out-of-three operation on the first scrambling code, the second scrambling code and the third scrambling code to obtain a final scrambling code; using the final scrambling code to conduct scrambling operation on the read formatted data. Because the three identical scrambling code tables are created in the FPGA and the final scrambling code is obtained by the two-out-of-three operation, the probability of the single event upset simultaneously occurring at the same locations of the three scrambling tables is extremely low, and therefore the capability and reliability of preventing the single event upset in parallel scrambling design are improved.

Provided is a semiconductor circuit device in which soft error resistance is enhanced while assuring the high-speed operation of an entire LSI circuit. A CAD device includes: means for identifying a signal transmission time of each signal transmission circuit of the LSI circuit; means for identifying an output inversion ratio upon radiation exposure of a flip-flop circuit of each signal transmission circuit; means for identifying a signal transmission circuit as a critical path; means for calculating a soft error ratio of the entire LSI circuit according to the signal transmission time, the output inversion ratio, and the clock cycle; and means for lowing the soft error ratio of the entire LSI circuit without changing the signal transmission time of the signal transmission circuit as the critical path when a predetermined soft error ratio is lower than the soft error ratio of the entire LSI circuit.

The invention discloses a register circuit with radiation reinforcing design, which comprises a first-stage master latch, a second-stage slave latch, a first phase inverter and a second phase inverter. The first-stage main latch is provided with two data inputs which are respectively from a data input di from a register and a complementary data input dib from the register; the first-stage main latch is provided with 1 clock input ck and two data outputs which are respectively a latch data ql and a complementary latch data qlb; the second-stage slave latch is provided with two data inputs which are respectively from the data output ql of the first-stage main latch and the complementary data output qlb of the first-stage main latch; the second-stage slave latch is provided one clock input ck and a complementary clock input ckn from the register; and the second-stage slave latch is provided with 2 data outputs which are respectively a register data rq of the register and a complementary register data rqb of the register. With the utilization of the register circuit with the radiation reinforcing design, the irradiation property of the register is enhanced, and no excessive area consumption is caused while the irradiation property of the register is improved.

The invention discloses an anti-radiation D flip-flop circuit based on three mutual-latching units. The anti-radiation D flip-flop circuit comprises a clock signal generation circuit, a D input filter circuit, C unit circuits, a voting circuit, a primary mutual-latching circuit and a secondary mutual-latching circuit. The C unit circuits include a first C unit circuit, a second C unit circuit and a third C unit circuit. Clock signals are generated after an external clock signal CK passes through the clock signal generation circuit, data signals are generated after an external data signal D passes through the D input filter circuit, data signals, output after the clock signals and the data signals pass through the primary mutual-latching circuit, the secondary mutual-latching circuit and the C unit circuits, passes through the voting circuit to output an output signal Q of a whole flip-flop. The anti-radiation D flip-flop circuit has the advantages that a three mutual-latching circuit reinforcement technology is adopted, output stability and reliability of the whole D flip-flop circuit can be guaranteed in case of overturning of the D flip-flop circuit due to interference such as radiation, and anti-radiation capability of the D flip-flop circuit is greatly improved.

The invention discloses a radiation-hardening trigger circuit based on a complex three-interlocking unit. The radiation-hardening trigger circuit is composed of a clock signal generating circuit, a D input filtering circuit, a C unit circuit, a voting circuit, and a main interlock. It consists of a storage circuit and a slave interlock circuit; the C unit circuit includes a first C unit circuit, a second C unit circuit and a third C unit circuit; the external clock signal CK generates the clock signal and external data through the clock signal generating circuit The signal D is input to the filter circuit through the D input filter circuit to generate the data signal after the master interlock circuit, the slave interlock circuit and the C unit circuit, the output data signal outputs the output signal Q of the entire flip-flop through the voting circuit. The technical scheme of the present invention adopts the complex three-interlock circuit to reinforce the flip-flop technology, which can ensure the stability of the output of the entire flip-flop circuit when the flip-flop circuit is disturbed by radiation and other interference and causes the circuit to flip, enhances its reliability, and greatly improves the flip-flop. Radiation resistance of the circuit.

The invention provides a data management method and device, a storage medium and an electronic device. The method comprises the steps that: state information of each physical block in the storage device is determined; under the condition that the physical blocks do not meet the target write-in mode, state information of the target physical blocks which do not meet the target write-in mode is stored in a first list, wherein the target write-in mode is used for indicating that the physical blocks support migration storage of multiple data; a migration list of the storage device is obtained, a virtual physical block bound to a target physical block on a corresponding migration node is determined according to the migration list, and information of the virtual physical block is stored in a second list, wherein the migration node is used for indicating the corresponding relation between the target physical block and the virtual physical block; and data writing management is performed on the storage device according to the migration list, the first list and the second list. The problem that the cost cannot be reduced while the reliability of the storage device is ensured in the prior art is solved.

The invention discloses a circuit for a correlator of a global positioning system, which comprises a 6-bit full adder, a register set, a latch set and a clock generating circuit. The 6-bit full adder is connected with the register set, which is connected with the latch set. The first clock signal from the clock generating circuit is taken as the switch controlling signal of the register set, the second clock signal from the clock generating circuit is taken as the reset signal of the register set and the switch controlling signal of the latch set. Between the 6-bit full adder and the latch set, a 14-bit counter is provided. The function control end C of the 14-bit counter is connected with the carry-over signal end of the highest place of the 6-bit full adder; the 14 output ends of the 14-bit counter are correspondingly connected with the 7th to 20th input end of the latch set. The first clock signal from the clock generating circuit is also used as the clock signal of the 14-bit counter, the second clock signal from the clock generating circuit forms a third clock signal after delaying by the delay unit, and the third clock signal is used as the reset signal of the 14-bit counter.

The invention relates to a spaceborne digital signal processor turning reinforcing method which is achieved through a spaceborne digital signal processor turning reinforcing system. The spaceborne digital signal processor turning reinforcing system comprises a digital signal processor (DSP) chip, an application specific integrated circuit (ASIC) chip, a programmable read only memory (PROM) and a static random access memory (SRAM). The method includes the steps of utilizing the design integrating outside slice running, error detection and correction (EDAC), an ASIC technology and a watchdog, meanwhile utilizing a radiation-proof ASIC technology to organically combine various anti-spatial-single-particle measures together, and to form a unique novel anti-single-particle reinforcing method. The spaceborne digital signal processor turning reinforcing method has the advantages of being capable of simplifying the system and improving inherent reliability, few in hardware resources, low in design complexity, simple in achieving, and capable of greatly reducing the rate of occurrence of single-particle events when the DSP chip runs in a bad radiation environment.

The invention relates to the technical field of integrated circuits, and relates to a SRAM storage unit reinforcement method based on a DICE structure and an SRAM storage array. The method includes: on the basis of the circuit design of the double interlocked memory cell DICE structure, adding an NMOS isolation tube between the NMOS transistors that can not share the source terminal and the drain terminal with the switching function, and the gate of the added NMOS isolation tube is added. Connect to GND. The problem of leakage current generated between adjacent NMOS transistors under the total dose of radiation in the existing layout technology is solved. The layout of sensitive MOS transistors in circuit design is crossed to increase the distance of sensitive nodes, thereby greatly reducing the probability of circuit flipping during single particle radiation. The effect of making the SRAM memory cells and arrays resistant to radiation without affecting the function is achieved.

A well-isolated anti-SEU multi-node inversion memory cell layout structure, comprising well isolation regions (201), (202), (203), DICE unit regions (101), (103), (105), (107), DICE units (102), (104), (106), (108). The well isolation region is arranged crosswise between the two DICE cell regions. Compared with the prior art, the present invention further increases the distance between sensitive node pairs while effectively separating all sensitive node pairs in the DICE memory cell structure, and the well isolation structure is also beneficial to reduce the distance between sensitive node pairs. The parasitic bipolar transistor effect and the charge sharing effect greatly suppress the multi-node turnover caused by SEU in the DICE unit, and greatly improve the anti-SEU performance of the radiation-resistant SRAM.