Multi-channel NAND FLASH error control method

Abstract

The invention provides a multi-channel NAND FLASH error control method based on the BCH and RAID-like technology. The method comprises the following steps: grouping input data according to a channel number N and then interleaving; performing XOR on the data of the N channels according to the channels to generate verification data; the check data and the N groups of channel data form N + 1 groups of channel data, and parallel scrambling is carried out on the N + 1 groups of channel data; BCH parallel coding is carried out on N + 1 groups of data, the data are partitioned according to the page length of FLASH, the coded data are stored in a storage array, and the storage array is composed of N + 1 FLASH storage chips and is in one-to-one correspondence with the N + 1 groups of data; the number of N + 1 groups in the storage array is read, parallel BCH decoding is carried out respectively, and a state of whether decoding is successful or not is given; performing parallel descrambling on the N + 1 groups of data; fault-tolerant control is carried out on N + 1 groups of data according to the state of whether decoding is successful or not; and carrying out de-interleaving recovery on the data subjected to error control. According to the method, design measures are taken from three dimensions of suppression, error correction and replacement, so that the bit error rate of the NAND FLASH is reduced.

Description

technical field [0001] The invention relates to an error control method, in particular to a multi-channel NANDFLASH error control method and system based on BCH and RAID-like technology. Background technique [0002] NAND Flash has the advantages of non-volatility, high reliability, small size, light weight, low power consumption, strong shock resistance, and wide operating temperature range. It has been widely used in various fields, especially aerospace. However, as NAND FLASH is used and the data storage time becomes longer, the data stored in it is prone to bit flips and random errors. In addition, as the number of erasing and writing of the FLASH block increases, the oxide layer gradually ages, and it becomes easier for electrons to enter and exit the storage unit, so the charge stored in it is prone to abnormalities, resulting in block failure. [0003] At present, the commonly used method adopts error code control, such as Hamming check, BCH, LDPC and other error con...

AI Technical Summary

Problems solved by technology

This method can meet the application occasions with low bit error rate. As the bit error rate increases, data error correction cannot be completed when the error correction capability of the algorithm is exceeded; secondly, the stronger the error correction capability of the algorithm, the higher its complexity. Unable to meet high-speed data error correction occasions

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