Parallel scrambling method for preventing single event upset in space

Abstract

Disclosed is a parallel scrambling method for preventing single event upset in space. The method comprises the steps of creating a first scrambling code table, a second scrambling code table and a third scrambling code table in an FPGA; adopting an 8-level shift register to dynamically generate a scrambling code sequence according to scrambling polynomial; writing the generated scrambling code sequence into the same addresses of the first scrambling code table, the second scrambling code table and the third scrambling code table according to bytes at the same time; reading formatted data, reading a first scrambling code from the first scrambling code table, reading a second scrambling code from the second scrambling table and reading a third scrambling code from the third scrambling code table at the same time, and conducting two-out-of-three operation on the first scrambling code, the second scrambling code and the third scrambling code to obtain a final scrambling code; using the final scrambling code to conduct scrambling operation on the read formatted data. Because the three identical scrambling code tables are created in the FPGA and the final scrambling code is obtained by the two-out-of-three operation, the probability of the single event upset simultaneously occurring at the same locations of the three scrambling tables is extremely low, and therefore the capability and reliability of preventing the single event upset in parallel scrambling design are improved.

Description

technical field [0001] The invention relates to the technical field of data transmission, in particular to a parallel scrambling method against spatial single event reversal. Background technique [0002] In the field of digital transmission, in order to facilitate timing recovery, the signal needs to be scrambled before transmission to change its transmission characteristics. Scrambling can limit the length of even "0" codes or "1" codes, and improve the signal bit timing content. At the same time, the original information is also fully randomized. The scrambling encoder can be realized by software or hardware design, and hardware implementation has higher encoding efficiency and does not need to occupy CPU resources. Therefore, in satellite communication, FPGA implementation is generally used. SRAM-type FPGA has the characteristics of rich logic resources, more internal RAM, high speed, and reconfigurability, and is the first choice for parallel scrambling design. Howeve...

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Problems solved by technology

[0006] Ma Yin, An Junshe, Wang Lianguo, Sun Wei, "Design of Anti-Single Event Flipping System Based on Scrubbing Space SRAM FPGA", Chinese Journal of Space Science, 2012 / 32(2)-270-07, for Xilinx Virtex-2 Series xc2v3000 devices propose a triple-mode redundancy plus refresh method to prevent the accumulation of single event upsets, but the FPGA device-level triple-mode redundancy will significantly reduce the device speed, which is not suitable for satellite high-speed data processing

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