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117results about How to "Reduce the number of masks" patented technology

Manufacturing method of TFT substrate and prepared TFT substrate

The invention provides a manufacturing method of a TFT substrate and a prepared TFT substrate. According to the manufacturing method of the TFT substrate, based on the characteristic of high visible light transmittance of a transparent metal oxide semiconductor material and doping processing is performed on a transparent metal oxide semiconductor, so that a transparent metal oxide conductor can be obtained, and at the same time, an active layer and a pixel electrode are formed, and therefore, the number of the times of photo masking can be decreased, production efficiency can be improved, and production cost can be reduced; in addition, based on only one semi-transparent photo mask, exposure and etching are performed, so that a common electrode, and a stack light shielding layer formed by a light shielding layer and a transparent conductive layer can be obtained, and therefore, the number of the times of photo masking can be further decreased; and the light shielding layer is arranged at the lower part of a TFT, so that the electrical stability of the TFT will not be affected by illumination. The TFT substrate of the invention is simple in manufacturing process and low in production cost; and the light shielding layer is arranged at the lower part of the TFT, so that the electrical stability of the TFT will not be affected by illumination.
Owner:TCL CHINA STAR OPTOELECTRONICS TECH CO LTD

Active matrix organic light emitting diode driving back plate and preparation method of active matrix organic light emitting diode driving back plate

The invention relates to an active matrix organic light emitting diode driving back plate and a preparation method of the active matrix organic light emitting diode driving back plate. The preparation method comprises the steps that a metal conducting layer is deposited and patterned on a substrate to be used as a grid electrode metal layer; an insulating film is deposited on the grid electrode metal layer to be used as a grid electrode insulating layer; a metal oxide film is deposited and patterned on the grid electrode insulating layer to be used as an active layer; another insulating film is deposited on the active layer to be used as an etching barrier layer; contact holes, the effective area of a memory capacitor and a source drain electrode region of a film transistor are patterned and defined on the etching barrier layer; and a conducting film is deposited and patterned on the etching barrier layer to be used as a source drain electrode layer of the film transistor. The memory capacitor uses the grid electrode metal layer as a lower electrode plate, uses the grid electrode insulating layer as a dielectric layer and uses the active source as a protecting layer of the grid electrode insulating layer, the effective area of the capacitor is defined by the etching barrier layer, and in addition, the conducting film layer is used as an upper electrode plate of the capacitor. The active matrix organic light emitting diode driving back plate and the preparation method have the characteristics that the preparation process is simple, and the cost is low. The important industry application value technology is realized.
Owner:GUANG ZHOU NEW VISION OPTO ELECTRONICS TECH

Array substrate and manufacturing method thereof, display panel and display apparatus

The invention discloses an array substrate and a manufacturing method thereof, a display panel and a display apparatus. In the prior art, a manufacturing technology of the array substrate is complex and a stray capacitance between a gate electrode and source and drain electrodes of a film transistor is large so that power consumption is large. By using the array substrate and the manufacturing method thereof, the display panel and the display apparatus of the invention, the above problems are solved. The array substrate comprises a gate metal layer, a gate insulation layer, an active layer, an etching barrier layer, a source and drain metal layer, a common electrode layer, a passivation layer and a pixel electrode layer which are successively formed on a substrate. An organic insulating layer is arranged between the etching barrier layer and the source and drain metal layer. The gate metal layer comprises the gate electrode, a gate line and a data line, wherein the gate line and the data line are arranged in a cross mode. The gate electrode is located below the active layer. The data line is separated into several segments by the gate line. The source and drain metal layer comprises a source electrode, a drain electrode and a plurality of first connecting lines. The source electrode and the drain electrode are located above the active layer and are connected to the active layer through first through holes of different positions respectively. The several segments of each data line are connected into one body through the plurality of first connecting lines.
Owner:BOE TECH GRP CO LTD

3D storage device

The present invention discloses a 3D memory device. The 3D memory device includes a gate stack structure, a plurality of channel pillars, and a plurality of dummy channel pillars; the gate stack structure includes a plurality of gate conductors and a plurality of interlayer insulating layers which are alternately stacked; the plurality of channel pillars penetrate the gate stack structure so as toform a transistor; and the plurality of dummy channel pillars pass through at least some of the gate conductors in the gate stack structure so as to provide support, wherein at least one of the dummychannel pillars is connected with a heat dissipation structure. According to the 3D memory device of the invention, the dummy channel pillars are connected to the heat dissipation structure, so thata heat dissipation path can be provided, and therefore, the yield and reliability of the 3D memory device can be improved.
Owner:YANGTZE MEMORY TECH CO LTD

Electroluminescence device, method of manufacturing electroluminescence device, and electronic apparatus

Provided is a method of manufacturing an electroluminescence device, in which a plurality of pixel forming regions is formed on a substrate, a light emitting element, in which an anode having a light transmission property, a light emission function layer including at least a light emitting layer and a cathode are laminated, is provided in each of the plurality of pixel forming regions, the pixel forming regions include a pixel forming region of first color and a pixel forming region of second color different from the first color, and the anode includes a first anode formed in the pixel forming region of the first color with a first thickness and a second anode formed in the pixel forming region of the second color with a second thickness, including: forming a first transparent conductive film in the pixel forming region of the first color with a thickness obtained by subtracting the second thickness from the first thickness; and forming a second transparent conductive film in the pixel forming region of the second color with the second thickness.
Owner:SEIKO EPSON CORP

Active matrix organic electro luminescence display device and manufacturing method for the same

An active matrix organic electro luminescent display (ELD) device comprises a substrate, first and second active layers formed of polycrystalline silicon on the substrate, first source and drain regions and second source and drain regions, the first source and drain regions neighboring the first active layer and the second source and drain regions neighboring the second active layer, a gate insulating layer on the first and second active layers, first and second gate electrodes on the gate insulating layer, a first inter layer on the first and second gate electrodes, an anode electrode and a capacitor electrode on the first inter layer, a first passivation layer on the anode electrode and the capacitor electrode, a power line on the first passivation layer, first source and drain electrodes on the first passivation layer, the first source electrode being connected to the first source region and the first drain electrode being connected to the first drain region, second source and drain electrodes on the first passivation layer, the second source electrode being connected to the second source region, the power line and the capacitor electrode and the second drain electrode being connected to the second drain region and the anode electrode, and a second passivation layer on the first source and drain electrodes and the second source and drain electrodes, the second passivation layer having a bank that exposes the anode electrode.
Owner:LG DISPLAY CO LTD

Fabrication method of low temperature poly-silicon array substrate, array substrate and display panel

The invention discloses a fabrication method of a low temperature poly-silicon array substrate, the array substrate and a display panel. The fabrication method comprises the steps of arranging a substrate, and forming a buffer layer on the substrate; forming a doped amorphous silicon film layer on the buffer layer by a mode of vapor deposition of a first mixed gas and a doped ion gas; dehydrogenizing the amorphous silicon film layer by a mode of vapor deposition of a second mixed gas; annealing the dehydrogenized amorphous silicon film layer so that doped ions are diffused to form a poly-silicon layer; and patterning the poly-silicon layer. By the fabrication method, the fabrication process of the low temperature poly-silicon array substrate can be effectively reduced, the investment of fabrication equipment is reduced, and the fabrication cost is further reduced.
Owner:WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD

Manufacturing technology of groove MOSFET device with masking films of decreased number

The invention relates to a manufacturing technology of a groove MOSFET device with masking films of a decreased number, which is characterized by comprising the following steps: selecting a substratematerial; growing an epitaxial layer on the substrate material; forming a trap area; forming a groove; growing a gate oxide in an oxidizing way; depositing polysilicon, and sculpturing the polysilicon; forming an N+ area. depositing an isolation medium layer; sculpturing a contact hole, and forming a P+ area; depositing a metal layer, and then photoengraving and sculpturing metal, thus the numberof the masking films of the produced groove MOSFET device is decreased to four.
Owner:KEDA SEMICON
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