Active matrix organic light emitting diode driving back plate and preparation method of active matrix organic light emitting diode driving back plate
A technology for light-emitting diodes and driving backplanes, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of unfavorable promotion and use, complicated manufacturing process, and high production cost, and achieve good industrial application value , Reduce the number of photomasks and improve the yield rate
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Embodiment 1
[0061] A method for preparing an active matrix organic light-emitting diode driving backplane includes the following steps.
[0062] Firstly, a metal conductive layer is deposited and patterned on the substrate as a gate metal layer.
[0063] The metal used to prepare the gate metal layer can be: aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), gold (Au), tantalum (Ta), chromium ( Cr) at least one of the simple substances or aluminum alloy. Usually, the above metal materials are deposited on the substrate by physical vapor deposition PVD (Physical Vapor Deposition) method to form a metal conductive layer.
[0064] The thickness of the metal conductive layer is 100nm to 2000nm. The metal conductive layer can be a single-layer metal film or a multi-layer film composed of a single-layer metal film. The single-layer metal film is any one of aluminum film, copper film, molybdenum film, titanium film, silver film, gold film, tantalum film, chromium film or...
Embodiment 2
[0091] A method for preparing an active matrix organic light-emitting diode driving backplane includes the following steps.
[0092] Such as figure 1 shown, in a SiO with 200 nm thick 2On the alkali-free glass substrate 1 of the buffer layer 2, a layer of Mo metal film with a thickness of 25 nm was deposited using PVD physical vapor deposition method, and then a layer of Al metal film with a thickness of 100 nm was deposited, and then a layer of Al metal film with a thickness of 25 nm was deposited. Mo metal film, three layers of metal film constitute the metal layer.
[0093] Then, the metal layer is patterned by a photolithography process to form a gate metal layer, and the gate metal layer is respectively used as a gate, a lower electrode of a capacitor, and a signal wire. figure 1 Among them, 3a is the gate of the thin film transistor, 3b is the lower electrode substrate of the storage capacitor, and 3c is the contact hole required for wiring between metal layers.
[00...
Embodiment 3
[0104] Such as figure 1 shown in a 50 nm thick Si 3 N 4 On the alkali-free glass substrate 1 of the buffer layer 2, Mo and Cu metal films are sequentially deposited by PVD method as the grid, the lower electrode of the capacitor and the signal wire. The thicknesses of the Mo and Cu metal films are 25 nm and 200 nm, respectively. Use a photolithography process to pattern it to form a metal layer, where 3a is the gate of the thin film transistor, 3b is the lower electrode plate of the storage capacitor, and 3c is the contact hole required for the wiring between the metal layers.
[0105] Such as figure 2 As shown, on the patterned gate metal, use PVD equipment to deposit Si with a thickness of 400 nm by reactive sputtering 3 N 4 As the gate insulating layer 4, then continue to deposit 30 nm metal oxide IZZO (In, Zn, Zr atomic ratio 1:1:0.1) as the active layer 5 without breaking the vacuum. Use Ruihong 304 photoresist as a photolithography mask, use dilute hydrochloric aci...
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