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66results about How to "Reduce hardware size" patented technology

Underwater sub-wavelength resolution ratio three-dimensional imaging method

The invention discloses an underwater sub-wavelength resolution ratio three-dimensional imaging method. The underwater sub-wavelength resolution ratio three-dimensional imaging method includes the following steps: (1) a sound signal is emitted; (2) acoustic lens wave beams are formed; (3) the sound signal is received and adjusted; (4) an image is processed and displayed. A two dimensional datum is obtained according to an imaging rule of an acoustic lens, a distance datum is obtained by utilizing an emission time and a receiving time, and a three dimensional underwater sound datum is obtained by combining with an electric signal received by a underwater sound sensor. The three dimensional underwater sound image datum undergoes image enhancement and image segmentation and a three dimensional image of a target is achieved by use of an open-sourcing visualization program library visualization toolkit (VTK). A reflected sound wave is focused through the acoustic lens and forms the wave beam. Hardware circuits of a normal imaging system are greatly reduced. A sub-wavelength image is achieved due to the characteristic of negative refraction of a phonon crystal. The novel underwater sound sensor with a mesoscopic pressure resistance is utilized, the underwater sound sensor responds to an underwater sound signal well, and a faint underwater signal can be effectively transformed.
Owner:ZHONGBEI UNIV

Control cycle synchronizer of triple-modular redundancy fault-tolerant computer

The invention relates to a control cycle synchronizer of a triple-modular redundancy fault-tolerant computer, which comprises single machines A, B and C, a voting circuit and control cycle interruption management modules arranged in the A, B and C, wherein the single machines A, B and C simultaneously input respective control cycle clocks to the voting circuit; the voting circuit uses an internal voting unit and wired-and logic to carry out a 2-out-of-3 vote on the input control cycles so as to produce a unified control cycle clock; the single machines A, B and C use the unified control cycle clock to response to control cycle interruption; and the control cycle interruption management modules turn off the control cycle interruption after the control cycle interruption is started, and turn on the control cycle interruption of the single machines A, B and C again after a certain time delay. By using the simple circuit design scheme, in the invention, the high-reliability control cycle synchronization control on the triple-modular redundancy fault-tolerant computer is realized, and all simplex fault modes including normally-0 or normally-1 faults as well as clock drift faults (including high-frequency oscillation and frequency downshift) can be tolerated.
Owner:BEIJING INST OF CONTROL ENG

Image recognition apparatus

An image recognition apparatus determines whether an image of a pedestrian is captured in a frame of video data captured by a vehicle mounted camera. A pre-processing unit determines a detection block from within a frame, and cuts out block image data corresponding to the detection block from the frame. Block data with a predetermined size that is smaller than the size of the detection block is created from the block image data. A neuro calculation unit executes neuro calculation on the block data, and calculates an output synapse. A post-processing unit determines whether a pedestrian exists within the detection block on the basis of the output synapse. When a pedestrian is detected, the post-processing unit creates result data, which is obtained by superimposing the detection block within which the pedestrian was detected onto the frame.
Owner:MEGACHIPS

Method and apparatus for power amplification

A power amplifier (101) amplifies a high-frequency signal. A coupler (102) monitors the signal power Pmoni amplified by the amplifier (101). A detector (103) carries out linear half-wave rectification of the input above the forward voltage of a diode, integrates it using an RC filter, and produces a detected voltage Vdet. A gain / offset amplifier (104) amplifies the detected voltage Vdet and / or applies an offset voltage to convert the detected voltage Vdet to a desired voltage, and the resulting voltage serves as the gate voltage of the power amplifier (101). As a result, power consumption in a low-power region of a power amplifier is reduced, and hardware is downsized.
Owner:PANASONIC CORP

ARIA encryption/decryption apparatus and method, and method of generating initialization key for the same

Disclosed is an Academy, Research Institute, and Agency (ARIA) encryption/decryption apparatus for encrypting and decrypting input data by repeating a plurality of rounds. The ARIA encryption/decryption apparatus includes a first register storing input data or an intermediate calculation value according to a first control signal; a second register storing a input round key for every round; an exclusive OR operation unit performing an exclusive OR operation on values stored in the first and second registers; a substitution unit substituting a result of the exclusive OR operation on a basis of an ARIA substitution algorithm; a diffusion unit diffusing a result of the substitution in the substitution unit on a basis of an ARIA diffusion algorithm if a current round is not a final round; and a control unit outputting the first control signal so that an output of the diffusion unit is used as the intermediate calculation value if the current round is the final round or an output of the substitution unit is used as the intermediate calculation value if the current round is the final round, and outputting an output of the exclusive OR operation unit as a result of the ARIA encryption/decryption.
Owner:ELECTRONICS & TELECOMM RES INST
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