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48results about How to "Reduce hardware area" patented technology

Shared parallel data reading-writing apparatus of multi memories among multi controllers, and reading-writing method of the same

The invention provides a shared parallel data reading-writing apparatus of multi memories among multi controllers, and a reading-writing method of the same. The shared parallel data reading-writing apparatus of multi memories among multi controllers includes a plurality of processor units and a plurality of storage units, wherein each storage unit is corresponding to each arbitration unit; each processor unit is corresponding to an address partition unit and a read data acquisition unit; aiming at the situation that the plurality of processor units access one storage unit at the same time, the arbitration unit can be used for carrying out arbitration management on a data operation request; and only the data operation request satisfying the preset conditions is selected; and the corresponding storage unit is used to execute data operation. As the processor units can directly access the storage units according to the addresses distributed by the address partition units, higher bandwidth can be provided; the operating performance of the processors can be satisfied; and the data access efficiency is greatly improved. Besides, the data exchange redundancy problem among the plurality of processors can be solved, so that the shared parallel data reading-writing apparatus of multi memories among multi controllers has wide market prospect in the integrated circuit field.
Owner:FUZHOU ROCKCHIP SEMICON

Real-time block floating point frequency domain four-route pulse compressor and pulse compression method thereof

The invention discloses a real-time block floating point frequency domain four-route pulse compressor and a pulse compression method thereof, and the problems that the existing pulse compression technology is long in time delay and poor in reusability are solved. The pulse compressor comprises an input data conversion module (1), a block floating point FFT module (2), a four-route matching multiplying module (3), a block floating point IFFT module (4) and an output data conversion module (5). A route of input serial data are converted by the first module (1) to four-route parallel block floating point data which are supplied to the second module (2) for FFT, after FFT, the data are supplied to the third module (3) for four-route matching multiplication, multiplication results are subjected to IFFT by the fourth module (4), and after IFFT, the data are converted by the fifth module (5) to be a route of serial fixed-point data or a route of serial floating-point data which are used as output results of pulse compression. The real-time block floating point frequency domain four-route pulse compressor has the advantages of being short in time delay and high in real-time ability, and can be used for real-time processing of radar signals.
Owner:XIDIAN UNIV

Hardware framework for two-dimensional discrete wavelet transformation

The invention provides a hardware framework for two-dimensional discrete wavelet transformation, which comprises a one-dimensional discrete wavelet transformation row module, a transposition module, a one-dimensional discrete wavelet transformation column module and a zoom module which are respectively connected in serial, image data are connected with the input end of the one-dimensional discrete wavelet transformation row module, and the zoom module outputs two-dimensional discrete wavelet transformation decomposing results. The framework has the advantages of high performance and low storage, and is suitable for realization of discrete wavelet transformation in JPEG2000 static image coding standards. By adopting the folding technology and the production line technology, the hardware framework provided by the invention reduces the number of operation units, shortens a key path of a system, and improves system performances. The one-dimensional discrete wavelet transformation row module and the one-dimensional discrete wavelet transformation column module in the hardware framework are scheduled by adopting row-based data flow, so that required middle caches can be greatly reduced, and further the area of an internal memory and the hardware area of the two-dimensional discrete wavelet transformation framework are reduced.
Owner:SOUTHEAST UNIV

Method for eliminating dead pixels in RAW-RGB image

The invention provides a method for eliminating dead pixels in an RAW-RGB image, which comprises the steps of converting R-pixels and B-pixels in an RAW-RGB image into G-pixels so as to convert the RAW-RGB image into a G-domain image, performing dead pixel judgment in the G-domain image, and then carrying out dead pixel elimination and restoration in the G-domain image. In the above process, the method can be implemented by only utilizing data of the current line where a dead pixel is located and a previous line, so that the volume of data required in the current technical scheme is greatly reduced, the time of data processing is reduced, and the possibility of real-time processing is increased. Meanwhile, the required hardware area is reduced, and the consumption of resources is lowered.
Owner:思特威(上海)电子科技股份有限公司

Piccolo encryption algorithm hardware achieving method

The invention discloses a Piccolo encryption algorithm hardware achieving method. The Piccolo encryption algorithm hardware can be achieved once by utilizing identical round operation in a repeated calling mode. The original r-1 round repeated calling is directly converted into r wheel repeated calling. Meanwhile, an RP-1 round displacement function is added on the r round circulation operation, and operation is conducted once to enable an output cipher to be correct. By means of the method, an original algorithm is not required to achieve again in the last rth round, the former repeated round function module can be directly multiplexed, and users only need to add the relatively simple RP-1 in the end. By means of the method, modules in the Piccolo encryption algorithm to be highly multiplexed, hardware achieving area is effectively saved, and meanwhile the encryption speed is increased.
Owner:HENGYANG NORMAL UNIV

Method and device for determining code phase of ranging code, and user terminal

The invention belongs to the technical field of communication and provides a method and device for determining a code phase of a ranging code, and a user terminal. The method comprises the steps of SA, obtaining discrete data; SB, obtaining carrier stripped data; SC, carrying out code matching operation according to the carrier stripped data and an initial position of sampling points, thereby obtaining a code matching result; SD, carrying out code phase search according to the code matching result and the locally copied ranging code; and SE, carrying out peak detection, if peaks are captured successfully, storing the captured peaks, adding the initial position of the sampling points and the step size x of the initial position, returning to the SC until the initial position of the sampling points is greater than the number p of the sampling points in a chip, and if the initial position of the sampling points is greater than the p, comparing p / x stored peaks, and finding the maximum peak, wherein the code phase of the ranging code is the code phase corresponding to the maximum peak. Through application of the method, the device and the user terminal, the code phase precision of the ranging code can be increased, and an area of a correlator is not increased.
Owner:ARKMICRO TECH

Hardware implementation device and method for Fruit-80 ultra-lightweight encryption algorithm

The invention discloses a hardware implementation device and method for a Fruit-80 ultra-lightweight encryption algorithm. The hardware implementation device comprises a key rotation function, a nonlinear feedback shift register, a linear feedback shift register, a key stream output function and a state control unit. The key rotation function is used for providing two key correlation bits; each of the nonlinear feedback shift register and the linear feedback shift register comprises a nonlinear feedback function and a linear feedback function; the key stream output function extracts the internal states of the nonlinear feedback shift register and the linear feedback shift register in each round, and generates a key stream for encryption; and the state control unit is used for coordinating the state updating of the nonlinear feedback shift register and the linear feedback shift register in the password stage of the device. According to the hardware implementation device and method disclosed by the invention, the hardware resource occupation of the Fruit-80 ultra-lightweight sequence cipher can be reduced, and the throughput rate of the Fruit-80 ultra-lightweight sequence cipher can be improved to the greatest extent.
Owner:SHANDONG UNIV

Hardware accelerator of convolutional neural network based on parallel multiplexing and parallel multiplexing method

The invention discloses a hardware accelerator of a convolutional neural network based on parallel multiplexing and a parallel multiplexing method. The hardware accelerator comprises a parameter storage module, an REG-FIFO module, a counting control module, an input multiplexing convolution operation module, an activation module and a pooling layer module. Wherein the parameter storage module is responsible for pre-storing picture parameters and trained weight parameters; the REG-FIFO module is responsible for generating an input matrix matched with the convolution kernel and reading matrix data; the counting control module is responsible for clock cycle counting and controls input and output of the REG-FIFO module according to the clock cycle counting. The input multiplexing convolution operation module is responsible for convolution operation of a convolution layer and a full connection layer; the activation module is responsible for output activation operation of the convolution layer and the full connection layer; and the pooling layer module is responsible for pooling operation output by the activated convolutional layer. The invention aims to realize convolutional neural network calculation with high operation parallelism, high data multiplexing and low hardware complexity.
Owner:HEFEI UNIV OF TECH

Display device and gate enabling method thereof

The invention discloses a display device. The display device comprises a display panel, a time schedule controller, a gate enabling frequency division controller and a gate driver, and the time schedule controller is used for generating a clock signal, a gate starting signal and a gate enabling signal. The gate enabling frequency division controller is coupled to the time schedule controller and is used for generating a plurality of frequency division gate enabling signals according to the clock signal, the gate starting signal and the gate enabling signal. The gate driver is coupled to the time schedule controller, the gate enabling frequency division controller and the display panel, and is used for generating a plurality of gate output signals to the display panel according to the clock signal, the gate starting signal and the plurality of frequency division gate enabling signals. According to the invention, the display device does not have a section of redundant pre-charging and discharging, so that waste of electricity can be avoided.
Owner:APLUS SEMICON TECH CO LTD
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