48results about How to "Reduce hardware area" patented technology

The invention provides a shared parallel data reading-writing apparatus of multi memories among multi controllers, and a reading-writing method of the same. The shared parallel data reading-writing apparatus of multi memories among multi controllers includes a plurality of processor units and a plurality of storage units, wherein each storage unit is corresponding to each arbitration unit; each processor unit is corresponding to an address partition unit and a read data acquisition unit; aiming at the situation that the plurality of processor units access one storage unit at the same time, the arbitration unit can be used for carrying out arbitration management on a data operation request; and only the data operation request satisfying the preset conditions is selected; and the corresponding storage unit is used to execute data operation. As the processor units can directly access the storage units according to the addresses distributed by the address partition units, higher bandwidth can be provided; the operating performance of the processors can be satisfied; and the data access efficiency is greatly improved. Besides, the data exchange redundancy problem among the plurality of processors can be solved, so that the shared parallel data reading-writing apparatus of multi memories among multi controllers has wide market prospect in the integrated circuit field.

An apparatus compensates image in a backlight local dimming system for estimating pixels of the image after backlight spreading of a plurality of backlight sources in the backlight local dimming system. The apparatus includes a block dimming value decision unit, a quality / power-saving priority decision unit, a temporal filter, a backlight spread approximation unit, and an image compensation unit. The block dimming value decision unit calculates an average value, a maximum value and a initial value for each image block. The quality / power-saving priority decision unit generates a backlight control signal based on the average value, the initial value, and two thresholds. The temporal filter adaptively generates a backlight pulse width modulation signal based on the backlight control signal. The backlight spread approximation unit generates a backlight spread image based on the backlight pulse width modulation signal. The image compensation unit compensates the image based on the backlight spread image.

A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.

A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained.

The invention discloses an image defective pixel detection method and apparatus. The method includes: obtaining an N*M pixel block of an image, arranging all pixel points in the pixel block in sequence to obtain a pixel value sequence, calculating a median of the pixel value sequence, and obtaining a pixel median; determining a specified small pixel value and a specified large pixel value from the pixel value sequence, calculating a first difference, and determining the pixel type of a current pixel point and calculating a second difference according to the relation between the current pixel point and the pixel median; and determining whether the current pixel point is a suspected defective pixel by determining whether the quotient of the second difference and the first difference is greater than a first preset error. The defective pixel is checked based on the attribute of the defective pixel of the image, compared with the conventional defective pixel detection method, the hardware area is reduced, pixel points of the image are checked one by one, more suspected defective pixels can be discovered, and the detection efficiency of the defective pixels is improved.

The invention discloses an HEVC (High Efficiency Video Coding) SAO (Sample Adaptive Offset) calculation method and an HEVC SAO calculation device. The device comprises an acquisition module, a serial number calculation module, an offset value determination module, a judgment module, an addition module, and an output module. First, offset values are calculated according to original pixels acquired by the acquisition module and reference pixels corresponding to the original pixel values. Then, the judgment module judges the pixel values or offset pixel values of the original pixels output and adopted finally according to the values of code flow control command parameters acquired. Thus, SAO decoding is completed by means of two-level pipelining. The speed of SAO decoding computation is increased. The steps of the SAO decoding computation process are greatly simplified. The hardware area of an SAO computation device is reduced in hardware circuit design, and therefore, the hardware cost is lowered. Therefore, the method and the device have a broad market prospect in the field of computer chips.