Hardware accelerator of convolutional neural network based on parallel multiplexing and parallel multiplexing method
A technology of convolutional neural network and hardware accelerator, which is applied in the field of artificial intelligence hardware design, can solve problems such as high computing parallelism, low hardware complexity, and large waste of resources, so as to improve network multiplexing, improve flexibility, shorten the effect of time
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[0091] In this embodiment, the convolutional neural network includes K layers of convolution layers, K+1 layers of activation layers, K layers of pooling layers, and 2 layers of fully connected layers; and the convolutional neural network is trained based on the MNIST handwritten digit set, get the weight parameter;
[0092] The convolutional neural network used in this embodiment is a handwritten digit recognition network, such as figure 1 As shown, its structure includes: 2 layers of convolution layers, 3 layers of activation layers, 2 layers of pooling layers, 2 layers of fully connected layers, using a 3 × 3 convolution kernel; except for the activation layer immediately after the convolution layer It has no effect on the feature map size. The other six-layer networks are arranged as follows: the first layer is a convolutional layer, the input feature size is 28×28×1, the weight matrix size is 3×3×1×4, and the length of the bias vector is is 4, the output feature size is ...
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