A unified architecture rendering shader based on dual-emitter VLIW

Abstract

The invention belongs to the technical field of graphics processing chip design, and discloses a unified structure rendering shader based on a double-emission VLIW. The shader is provided with a parameter descriptor circuit for analyzing and processing input command flow information; a shading state control circuit which determines the processing contents of different pipeline stages of the unified shader according to the rendering information of the polygon to be rendered; a dual-transmit VLIW processor circuit which performs corresponding graphics task processing or general-purpose computingprocessing according to the current state and configuration parameters; a texture filter circuit which performs bilinear interpolation or trilinear interpolation filtering on the texture texture texture values read from the texture memory under the configuration of the VLIW processor circuit. The invention can reduce the complexity of hardware design and the conversion time of the data between the vertex shader and the pixel shader in the traditional architecture. The unified shader has the advantages of simple structure, small hardware area and good real-time performance.

Description

technical field [0001] The invention belongs to the technical field of graphic processing chip design, and in particular relates to a rendering shader with a unified architecture based on double-emission VLIW. It also relates to a graphics processing unit circuit with a unified architecture, in particular to a basic dual-issue VLIW processor for vertex coloring and pixel coloring, based on the multiplexing of floating-point computing units and transcendental function computing units, and adopting a basic SIMD architecture circuit structure. Background technique [0002] At present, the existing technologies commonly used in the industry are as follows: [0003] In the IMR rendering architecture, each object submitted for rendering will be executed immediately and pass through the entire rendering pipeline. It is precisely because of this simple and direct design method that each submitted rendering command will be executed immediately, and when the The rendering command is...

AI Technical Summary

Problems solved by technology

This means that if there are a large number of vertices in a frame, it is difficult for the on-chip cache to store so much vertex information and Tile-list information, and it has to rely on external memory for storage, which will generate additional bandwidth consumption

[0012] In the mobile GPU implemented with this split architecture design, the number of vertex shaders and pixel shaders is certain, but due to the different rendering commands processed , the two can only perform specific operations on different forms of input data, and it is easy to have the problem that the two shader computing resources cannot be fully utilized at the same time during the rendering process

[0013](1) In the prior art, the use of a unified architecture to design mobile terminal graphics processors cannot well reduce the hardware design complexity and data transfer between processor cores conversion time

[0014] (2) It is difficult to achieve high hardware resource utilization between vertex shader and pixel shader processing

[0016] Difficulty lies in: 1. Perform graphics vertex data processing and pixel data processing on the same shader, and design a unified hardware architecture and compatible instructions The set is a design problem; 2. Both the vertex processing program and the pixel processing program will be processed in the same shader, so judging and balancing the processing scheduling of the shader for these two programs has become a design problem for the unified shader

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