32results about How to "Optimize write performance" patented technology

The invention relates to an SRAM memory unit, a memory array and a memory. The SRAM storage unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first pass transistor, a second pass transistor, a first double-gate PMOS transistor, and a second double-gate PMOS transistor . The invention can solve the problem that the writing operation failure of the SRAM storage unit may exist.

The invention discloses a method for scanning error bits. The method comprises the following steps: S1, averagely dividing a first data partition of a storage unit into N equal second data partitions; S2, forming a third data partition by using the second data partitions, scanning the third data partition and setting the permissible number of the error bits; S3, comparing the actual number of the error bits of the third data partition with the permissible number of the error bits, if the actual number of the error bits is greater than the permissible number of the error bits, executing step 4, if not, executing step 5; S4, carrying out one-time programming operation on the storage unit and returning to carry out the step S3; and S5, recording the current actual number of the error bits of the third data partition. According to the method, the qualification rate of storage chips can be adjusted through modifying the setting conditions; the corresponding data region and the error correcting capability of the own ECC (Error Correction Code) of a controller can be adjusted on the basis of final statistical results; and therefore, a better write performance is obtained.

The invention provides a split grating flash memory and a manufacture method thereof. The split gate flash memory comprises a semiconductor substrate, a gate oxide and split structure units, wherein the gate oxide is positioned on the surface of the semiconductor substrate; and the split structure units are positioned on the gate oxide. Each split structure unit is provided with a floating gate, a gate medium layer, a control gate, a first side wall layer, a second side wall layer, a third side wall layer, a word line and side walls, wherein the floating gate is positioned on the gate oxide, and the surface of the floating gate is in a cambered shape with an inclined angle; the gate medium layer is positioned on the surface of the floating gate; the control gate is positioned on the gate medium layer; the first side wall layer is positioned on the control gate; the second side wall layer is positioned on the inner side wall of the control gate; the third side wall layer is positioned in the first side wall, the second side wall layer, the gate medium layer and the inner side wall of the floating gate; the word line is positioned between two split structure units and fills a gap; and the side walls are positioned at the outside walls of the split structure units. The invention improves the performance of flash memory erasure or writing and the electric performance of the flash memory.

The present invention overcomes the limitations of the existing RAID technology on the storage medium and storage space of each sub-disk, and provides a high-performance and high-reliability wide-striped disk array based on asymmetric hybrid disk mirroring and a data storage method thereof. The disk array includes at least two physical storage pools, each physical storage pool is composed of the same storage medium, the disk array contains at least two different storage media, and the disks of at least two storage media are used to form a mirror disk in a mirroring manner, A plurality of mirror disks form a wide-stripe mirror group; the disk array also includes a controller connected to each physical storage pool for controlling data writing and reading. The data is stored in at least two physical storage pools, and the data is read from the physical storage pool with a faster reading speed.

The present invention provides a method for writing data based on memory replacement, the realization process of which is as follows: setting up the memory structure, independently designing the part used for data reading and writing in the memory, and integrating two integrated circuits with exactly the same capacity ; Perform memory switching, the system starts in general mode when it is just started, and after running for a period of time, the system-related applications are completely loaded, and the memory management unit detects the capacity used by the stack according to the switching mode set by the system, and then according to The actual capacity plus a certain amount of redundancy sets the stack area, then detects the memory used for reading, and adds a certain amount of redundancy to set the read memory, and the remaining memory is completely mapped to the write memory to complete the memory switching process . Compared with the prior art, the method for writing data based on memory replacement can smooth the entire writing process by replacing the memory when writing files, improve the writing performance, have strong practicability, and be easy to popularize.

There is provided a tape recording apparatus system capable of improving writing performance and maintaining tape recording density, for a multiple data writing request accompanied by a lot of synchronization requests from a host. The system is a tape storage system including two or more tape drives each of which has a tape mounted thereon and is provided with a buffer divided in fixed-length segments, and connected to a host that sends multiple data and a synchronization request at a predetermined timing to these tape drives. This tape recording system is provided with: a tape drive connected to the host, receiving the multiple data sent from the host, and, when the segment of the buffer is accumulated and filled with data, writing the accumulated data onto a tape; and another tape drive connected to the tape drive, receiving the multiple data sent from the host via the tape drive, and dumping a predetermined number of data accumulated in the segments onto a tape at a timing of receiving the synchronization request.

The invention relates to an SRAM memory unit, a memory array and a memory. The SRAM storage unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first pass transistor, a second pass transistor, a first double-gate NMOS transistor, and a second double-gate NMOS transistor . The invention can solve the problem that the writing operation failure of the SRAM storage unit may exist.

The invention discloses a storage system and a method for implementing the same. The storage system comprises a disc array and a storage control device, wherein the disc array comprises at least one solid-state disc and at least one non-solid-state disc; the storage control device is configured to respond to entering into a clearing mode, scanning and moving data blocks in the at least one non-solid-state disc in the disc array to form more continuous idle blocks. The storage system provided by the invention has better reading and writing performance, higher data reliability and usability and lower cost.