A way to scan for error bits

Abstract

The invention discloses a method for scanning error bits. The method comprises the following steps: S1, averagely dividing a first data partition of a storage unit into N equal second data partitions; S2, forming a third data partition by using the second data partitions, scanning the third data partition and setting the permissible number of the error bits; S3, comparing the actual number of the error bits of the third data partition with the permissible number of the error bits, if the actual number of the error bits is greater than the permissible number of the error bits, executing step 4, if not, executing step 5; S4, carrying out one-time programming operation on the storage unit and returning to carry out the step S3; and S5, recording the current actual number of the error bits of the third data partition. According to the method, the qualification rate of storage chips can be adjusted through modifying the setting conditions; the corresponding data region and the error correcting capability of the own ECC (Error Correction Code) of a controller can be adjusted on the basis of final statistical results; and therefore, a better write performance is obtained.

Description

technical field [0001] The embodiment of the present invention relates to the field of storage technologies, and in particular to a method for scanning error bits. Background technique [0002] Non-volatile flash memory (nor flash / nand flash) is a very common memory chip, which has the advantages of random access memory (RAM) and read-only memory (Read-Only Memory, ROM). It will not be lost. It is a memory that can be electrically erased and written in the system. At the same time, its high integration and low cost make it the mainstream of the market. The Flash chip is composed of thousands of internal storage units, multiple storage units form a page, and multiple pages form a block. It is precisely because of this special physical structure that in nor flash / nand flash, the page Read and write data, and erase data in units of blocks. [0003] Due to the various crosstalk characteristics of the memory chip, error bits will appear during use. In order to ensure the stabil...

AI Technical Summary

Problems solved by technology

However, when the actual controller uses ECC, it will arrange memory data and store ECC according to its own needs. During the test, it is impossible to set the corresponding test conditions according to the number of error bits in the storage unit. If the test conditions are set too loosely, the given The ECC error correction capability cannot match the actual read cycle of the memory cell. If the test conditions are set too tight, it will affect the yield rate of the memory chip.

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