SRAM memory cell, storage array and memory

Abstract

The invention relates to a SRAM memory cell, a storage array and a memory. The SRAM memory cell comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first transmission transistor, a second transmission transistor, a first double-grid NMOS transistor, and a second double-grid NMOS transistor. According to the invention, the possible failure problem of write-in operation of the SRAM memory cell can be solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM memory unit, a memory array and a memory. Background technique [0002] SRAM (Static Random Access Memory, hereinafter referred to as SRAM) has the advantages of high speed, low power consumption and compatibility with standard processes. It is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, multimedia players) and other fields. [0003] The most common SRAM storage unit is 6T unit, such as figure 1 As shown, the SRAM storage unit includes: a first PMOS transistor ML0, a second PMOS transistor ML1, a first NMOS transistor MPD0, a second NMOS transistor MPD1, a third NMOS transistor MPG0 and a fourth NMOS transistor MPG1. [0004] The first PMOS transistor ML0 , the second PMOS transistor ML1 , the first NMOS transistor MPD0 and the second NMOS transistor MPD1 form a bistable circuit, and the bistable circuit forms a...

AI Technical Summary

Problems solved by technology

[0025] The technical problem solved by the present invention is to provide a SRAM storage unit to solve the problem of write operation failure that may exist in the SRAM storage unit

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