259results about How to "Increase capacitance density" patented technology

An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously.

An electric double layer capacitor includes, contained in a casing, an electrolyte, a positive electrode and a negative electrode each being an electrode containing carbon black, to form an electric double layer at the interface with the electrolyte, and a separator interposed between the positive electrode and the negative electrode. At least one electrode of the positive electrode and the negative electrode has protruded portions or bent portions formed continuously in the height direction against the bottom face of the casing. Further, a space due to the height of the protruded portions or the bent portions is formed between the at least one electrode and the separator.

An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.

A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

An organic/inorganic oxide mixture has high capacitance density so as to realize a capacitor material that can be self-contained in a substrate. The mixture film made of inorganic oxide particle has a mean particle size of less than 90 nm dispersed in organic polymer, of which relative dielectric constant is more than 10 and thickness is less than 900 nm.

The invention discloses a plate capacitor and polymer-matrix composite dielectric material which can be filled with reactive nano particles, belonging to the technical field of the electronic materialand the electronic component. The reactive nano particles are conductive nano particles in core shell structures, the surface of each conductive nano particle is coated with a layer of insulating coating, and the surface of the insulating coating can carry reactive functional groups. The nano particles can be organically combined with polymer through the reactive functional groups and can be evenly dispersed in the matrix of the polymer. The polymer-matrix composite dielectric material which can be filled with the conductive nano particles can be used as the dielectric layer and flexible foilsheets can be used the upper electrode and the lower electrode of the plate capacitor.

A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers of an IC, with each unit cell comprising a center conductor and a conducting ring which surrounds the center conductor. Each array comprises a plurality of unit cells, tiled on a given IC layer at a predetermined pitch. The arrays are arranged vertically such that adjacent vertical arrays are offset in the x and y dimensions by a predetermined fraction—preferably ½—of the unit cells' pitch. The structure includes vias arranged to interconnect the arrays such that each center conductor is connected to a conducting ring of the array immediately above and/or below the center conductor, and such that each conducting ring is connected to a center conductor of the array immediately above and/or below the conducting ring.

The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.

An electronic assembly (98) includes a substrate (20), a capacitor having first and second conductors (38,54) formed over the substrate, a first set of conductive members (76) formed over the substrate and being electrically connected to the first conductor of the capacitor, and a second set of conductive members (78) formed over the substrate and being electrically connected to the second conductor of the capacitor.

The invention relates to a vertical-type capacitor structure and a manufacturing method of the vertical-type capacitor structure, and belongs to the technical field of micro-electronic passive devices. The vertical-type capacitor structure structurally and specifically comprises a deep-groove structure, insulating layers, conducting layers and a dielectric layer, wherein the deep-groove structure is located inside a wafer substrate, the insulating layers and the conducting layers are sequentially deposited on the inner side wall of a deep groove, and the dielectric layer is filled between the conducting layers. The insulating layers, the conducting layers, the dielectric layer and the deep groove are the same in height. On the basis of the principle that the area of a capacitor is expanded in the direction perpendicular to the substrate, the area of an plate electrode in the perpendicular direction is utilized, the processes such as sputtering and electroplating are adopted to manufacture a metal plate electrode, and the plate electrode is made of low electrical resistivity materials, like metal. With the combination of a silicon through hole technology, the vertical-type capacitor with a large depth-to-width ratio is achieved. With the combination of a substrate back thinning technology, the vertical-type capacitor structure penetrates through the substrate, the vertical-type capacitor structure can be used as a high-frequency channel between multi-layer chips, the area of the plate can be greatly saved, and the integration level of an integrated circuit is improved.

The invention discloses a linear secure high-energy-density supercapacitor and a preparation method thereof. The method comprises the following steps of 1) respectively taking two conducting fibers which are in core-shell structures as the anode and the cathode of the linear supercapacitor and twisting the two conducting fibers together to form the intertwisted anode and cathode; 2) coating gel electrolyte onto the surface of the anode and cathode and curing the gel electrolyte to form a gel electrolyte layer; 3) connecting the intertwisted anode and cathode coated with the gel electrolyte layer with lead wires respectively through conductive adhesive bonding or tin scolding methods. The preparation method is simple and is low in cost, strong in applicability, and suitable for large-scale industrial production. The produced linear supercapacitor is characterized by lightweight, security, high energy density, good flexibility, intertwining capability, and the like. The produced linear supercapacitor is applicable to flexible energy storage devices, lightweight portable electronic devices, military-use electronic clothes, and other fields.

A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

A MEMS pressure sensor device comprises a sensor element positioned on top of a carrier and a cavity. The sensor element hermetically seals the cavity. An electrode is coupled to the cavity that forms a pressure transducer together with the sensor element. The cavity is created by a density changing material.