101 results about "Time to digital conversion" patented technology

A time correlated single photon counting system having a time to digital converter triggered by a laser fire event detector and the reception of a single photon. The system may be used for chemical agent detection based on Rayleigh scattering using optical time domain reflectometry techniques. The system may also be used for Raman detection using frequency to time transformations.

Methods and systems for performing three dimensional LIDAR measurements with an integrated LIDAR measurement device are described herein. In one aspect, a return signal receiver generates a pulse trigger signal that triggers the generation of a pulse of illumination light and data acquisition of a return signal, and also triggers the time of flight calculation by time to digital conversion. In addition, the return signal receiver also estimates the width and peak amplitude of each return pulse, and samples each return pulse waveform individually over a sampling window that includes the peak amplitude of each return pulse waveform. In a further aspect, the time of flight associated with each return pulse is estimated based on a coarse timing estimate and a fine timing estimate. In another aspect, the time of flight is measured from the measured pulse due to internal optical crosstalk and a valid return pulse.

A time to digital converter includes: a delay circuit having a plurality of delay stages that delay an input clock signal in multiple stages, at least one of the delay stages being a variable delay stage; a plurality of flip flops that capture outputs of the delay stages corresponding thereto in a one-to-one relation in response to input of a reference signal; an edge detecting circuit that detects changing edges of respective outputs of the flip flops; a counter circuit that counts a number of edges detected by the edge detecting circuit; and a control circuit that controls a delay amount of the variable delay stage according to the number of edges counted by the counter circuit.

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

The invention discloses a dual-loop DLL-based three-segment type high-precision time-to-digital conversion method and circuit. According to a measured time segment, a high-middle-low combined segmental type quantization method is adopted. A high-segment bit counting type quantizer in three-segment type TDC (time-to-digital conversion) is driven by a high-frequency stabilizing clock which is inputted from the outside, so that a wide-range stable distance measuring range can be realized; a middle-segment bit TDC is formed by a first DLL voltage controlled delay chain; high-segment bit subdivision can be realized through an asynchronous sampling mode, and repeatable uniform phase distinguishing can be accomplished in a stable clock period; a phase position at a termination time point is decoded, so that a middle-segment quantization function can be accomplished; and according to quantization errors generated by time-to-digital conversion in a middle-segment bit, error time is extracted, a low-segment bit accomplishes further quantization processing, and therefore, higher measurement precision can be realized.

The present disclosure includes a method that includes generating a decoded output signal that corresponds to reflected light received by a plurality of single photon avalanche diodes (SPAD) by removing ambient light from a plurality of SPAD array output signals. The removing of ambient light including synchronizing the plurality of SPAD array output signals by using a plurality of parallel time to digital converters, each time to digital converter outputting a synchronized SPAD array output signal, determining a plurality of flexible thresholds for each one of the synchronized SPAD array output signals, comparing current data on the synchronized SPAD array output signals with the respective ones of the flexible threshold in a filter, and outputting the first output signal.

Time to digital converters (TDCs) with high resolution are disclosed. The TDC includes a first time to digital converting module, a selection and time amplifying module, a second time to digital converting module and a decoder, and is applied in estimating a time difference between a first signal and a second signal. As the delay time of the delay units of the time to digital converting modules is the unit of the time difference measurement, the first and second time to digital converting modules are responsible for the integral portion and the fractional portion of the estimated time difference, respectively. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding an error detection circuit to the TDC, the possible metastable problem can be prevented.

The invention discloses a three-segment time-to-digital conversion circuit based on a phase-locked loop. Accurate counting clocks of a plurality of different frequencies and a plurality of uniform split phases are provided for a time-to-digital converter (TDC) through the phase-locked loop, so that accurate measurement of measured time by the TDC is ensured; the phase-locked loop is a three-order type-2 phase-locked loop, and comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider and an auxiliary state detection circuit; the TDC is a three-segment TDC including a high segment, a middle segment and a low segment; and the high segment of the TDC is provided with a 7-bit linear shift register. According to the three-segment time-to-digital conversion circuit, the phase-locked loop has the advantage of providing stable clocks of different frequencies and uniform phases, so that rough counting and fine quantitation and further fine quantitation of a measured time amount are finished; wide-range measurement is finished; and the measuring accuracy is ensured at the same time. Meanwhile, initial-phase time is measured at a same resolution, so that initial-phase time errors are eliminated, and the resolution and the measuring accuracy are kept constant at the same time.

A circuit device includes a time-to-digital conversion circuit, to which a first clock signal generated using a first resonator, and having a first clock frequency, and a second clock signal generated using a second resonator, and having a second clock frequency different from the first clock frequency are input, and which converts time into a digital value using the first and second clock signals, and a PLL circuit adapted to perform phase synchronization between the first and second clock signals.

A detector (22) detects an event. First and second time-to-digital converters (TDCs) (70, 72) generate first and second time stamps (TS1, TS2) for the detection of the event. The first TDC and the second TDC are both synchronized with a common clock signal (62) that defines a fixed time offset between the second TDC and the first TDC. An autocalibration circuit (120) adjusts the first TDC and the second TDC to keep the time difference between the second time stamp and the first time stamp equal to the fixed time offset between the second TDC and the first TDC. The detector may be a detector array, and trigger circuitry (28) propogates a trigger signal from a trigger detector of the array of detectors to the first and second TDC's. Skew correction circuitry (132, 134, 136, 142, 60, 162) adjusts a timestamp (TS) based on which detector is the triggering detector.

The invention discloses a wireless low-jitter transmission method for a digital asynchronous pulse, which belongs to the wireless pulse transmission and communication field. The wireless low-jitter transmission method for the digital asynchronous pulse is especially suitable for the wireless low-jitter transmission of radar pulse. Pulse shaping is carried out on a transmitting end; the pulse is subjected to rough sampling and fine sampling by utilizing a reference clock and a time-to-digital conversion circuit; the digitalized time information obtained by sampling is coded and modulated; on a receiving end, the steps of demodulating and decoding are finished by utilizing a synchronized reference clock; rough sampling information and fine sampling information are recovered; according to the rough sampling information and the fine sampling information, a clock period corresponding to a pulse signal to be recovered is determined; the rising edge of the corresponding clock period is delayed for a certain period of time by utilizing a programmable delay circuit to obtain a pulse rising edge to be recovered; the pulse rising edge is widened and judged; and finally, a low-jitter pulse signal is output. According to the wireless low-jitter transmission method for the digital asynchronous pulse, the transmitting end pulse can be favorable recovered, the wireless low-jitter transmission method has a low requirement on a clock in a system, and the main circuit component is realized by adopting an FPGA (field programmable gate array) or ASIC (application specific integrated circuit), thereby being low in designing and debugging difficulty.

A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.

There is provided a bidirectional readout circuit for detecting direction and amplitude of an oscillation sensed at a capacitive microelectromechanical system (MEMS) accelerometer, the bidirectional readout circuit converting capacitance changes of the capacitive MEMS accelerometer into a time change amount by using high resolution capacitance-to-time conversion technology and outputting the time change amount as the direction and the amplitude of the oscillation by using time-to-digital conversion (TDC) technology, thereby detecting not only the amplitude of the oscillation but also the direction thereof, which is capable of being applied to various MEMS sensors.