37 results about "Parallel software" patented technology

A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.

A method for race detection in parallel software, including performing an execution of software under test (SUT), the SUT having an expected outcome. The method further includes detecting a race condition in the SUT responsive to a first interleaving generated during the execution, replaying the first interleaving to a start-point of the race condition, and imposing a second interleaving at the start-point of the race condition. The method also includes determining a second-execution outcome of the SUT responsive to the second interleaving, and comparing the expected outcome with the second-execution outcome.

This invention teaches a way of implementing formally verified massively parallel programs, which run efficiently in distributed and shared-memory multi-core chips. It allows programs to be developed from an initial abstract statement of interactions among parallel software components, called cells, and progressively refine them to their final implementation. At each stage of refinement a formal description of patterns of events in computations is derived automatically from implementations. This formal description is used for two purposes: One is to prove correctness, timings, progress, mutual exclusion, and freedom from deadlocks / livelocks, etc. The second is to automatically incorporate into each application a Self-Monitoring System (SMS) that constantly monitors the application in parallel, with no interference with its timings, to identify and report errors in performance, pending errors, and patterns of critical behavior. This invention also teaches a way of organizing shared-memory for multi-processors that minimizes memory interference, protects data and increases execution efficiency.

The invention discloses a server group system with single system reflection, including a hardware layer, a distributed virtual machine monitor layer and an operation system layer; wherein, the hardware layer includes a plurality of nodes, a CUP of the nodes supports the hardware virtualization and the nodes are connected via a high-speed network. The distributed virtual machine monitor layer is provided with a virtual machine monitor on the hardware of each node and the virtual machine monitors of the nodes are communicated through bottom communication software and the high-speed network. The operation system layer supports various commercial operation systems of cc-NUMA and existing various cc-NUMA-oriented paralleling software can be operated on the system without modification. Based on the virtualization of the hardware resources, the system achieves the single system reflection of the server group system. The server group system provided by the invention has the advantages of good transparency, high performance, wide application range, moderate realizing difficulty, etc.

A passive tracking system is provided with a plurality of ultrawideband (UWB) receivers that is asynchronous with respect to a UWB transmitter. A geometry of the tracking system may utilize a plurality of clusters with each cluster comprising a plurality of antennas. Time Difference of Arrival (TDOA) may be determined for the antennas in each cluster and utilized to determine Angle of Arrival (AOA) based on a far field assumption regarding the geometry. Parallel software communication sockets may be established with each of the plurality of UWB receivers. Transfer of waveform data may be processed by alternately receiving packets of waveform data from each UWB receiver. Cross Correlation Peak Detection (CCPD) is utilized to estimate TDOA information to reduce errors in a noisy, multipath environment.

A method and associated systems for dynamic container deployment with parallel layers. A processor creates an image file by processing each instruction of an image-container file in sequential order, where each instruction adds a layer to the image file that identifies either an unconditional or a parallel software layer of a container. Each unconditional layer is assigned a unique level but parallel layers may share a same level. The processor then deploys an instance of a container by deploying layers of the image file to the container in the order in which they were created by the image-creation file. If an image-file layer is marked as parallel, it is deployed only if an associated condition is satisfied, such that no two deployed layers have the same level.

Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development.

A non-intrusive debugging framework for parallel software based on a super multi-core framework is composed of a plurality of core clusters. Each of the core clusters includes a plurality of core processors and a debug node. Each of the core processors includes a DCP. The DCPs and the debug node are interconnected via at least one channel to constitute a communication network inside each of the core clusters. The core clusters are interconnected via a ring network. In this way, the memory inside each of the debug nodes constitutes a non-uniform debug memory space for debugging without affecting execution of the parallel program, such that it is applicable to current diversified dynamic debugging methods under the super multi-core system.

The invention discloses a parallel programming model system of DAG oriented data driving type application and a realization method. The parallel programming model system of DAG oriented data driving type application comprises a DAG mode chart module, a user application program module and a DAG runtime system module, wherein the DAG mode chart module comprises a DAG mode chart bank; the user application program module is used for user initialization setup and confirmation of specific parallelization algorithm; and the DAG runtime system module comprises a main thread and a thread pool. The main thread is used for analyzing and updating the DAG mode chart, issuing and dispatching data block, and controlling fault-tolerance; the thread pool comprises a thread pool queue buffer zone and a work thread, wherein the thread pool queue buffer zone is a data interface for the main thread and the work thread, the work thread is used for constantly acquiring computing tasks from the queue buffer zone and carrying out computing. Compared with the prior art, the invention decreases difficulty in designing and developing a parallel computing application program for non-computer professionals, shortens development period of parallel software, and enables the completed parallel computing application program to have more reasonable structure and more optimized performance.

The present invention has been made to provide a software verification program, a software verification apparatus, and a software verification method capable of reducing verification cost of concurrent / parallel software.A software verification program allowing a computer to execute verification of software including a library 11 and a program that uses a library 21 to operate in a concurrent or parallel manner, comprises: a shared element utilizing part extraction step that extracts a part at which a shared element, which is an element that is defined in the library 21 and which can be used by the program 22, is used in the program 22; and a condition verification step that verifies based on a thread-safe condition defined in the library 21 for the each shared element whether a shared element in the shared element utilizing part extracted by the shared element utilizing part extraction step satisfies the thread-safe condition.

A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.

The invention relates to the technical field of parallel computing, in particular to a parallel computing component and method and a corresponding parallel software development method and system. The parallel computing component comprises a parallel computing component interface, a data distribution storage unit, a data parallel communication unit and a numerical parallel computing unit, wherein the parallel computing component interface is used for providing numerical data for other units and feeding back numerical data subjected to numerical computation; the data distribution storage unit is used for storing a data field and the numerical data received from the parallel computing component interface in a private memory space of a progress; the data parallel communication unit is used for copying data fields from private memory spaces of other progresses and storing the data fields to a local progress; the numerical parallel computing unit is used for computing the numerical data of the local progress independently according to a numerical analog computation process of a numerical algorithm. By means of the method and system, the reusability, maintainability and extendibility of a software module can be improved remarkably, and the computing efficiency of application software is improved remarkably.

A Method and System for Parallel Operation and Control of Legacy Computer Clusters is disclosed. Also disclosed is a system that permits the creation of a cluster computer using the legacy operating systems already existing on the computing devices. The system is further be able to seamlessly operate over a standard wide are network, such as the “Internet,” as well as over local area networks. The system further permits the individual computers to operate either as part of the cluster, or on local operations, without any need for modification to the other computers involved in the cluster. Still further, the system utilizes standard TCP / IP format for all internodal messaging. Also, the system maintains performance “grades” for each cluster node, either by node self-grading, or by node reporting, such that the user can select which nodes to participate in a particular parallel application. The system is compatible with non-parallel software applications, and will preferably use MPI standards for internodal communications. Finally, each cluster's parallel computing control application may monitor users' cluster use time for the purpose of potentially limiting access to the cluster due to exhaustion of that user's allotted time

The invention discloses a Harris corner detecting parallel software system based on the design idea of a Graphics Processing Unit (GPU). The time-consuming image Gaussian convolution smoothing filtering part in calculation is improved to a Single Instruction Multiple Thread (SIMT) mode through a plurality of threads, and the whole process of image corner detecting is finished on a Compute Unified Device Architecture (CUDA) through a shared memory, a constant memory and a lock page internal storage mechanism in the GPU. Corners detected by the software system are distributed evenly, and good effects in the aspects of corner extracting and precise positioning are achieved. Compared with a serial algorithm based on a CPU, a Harris corner detecting parallel algorithm based on the GPU can obtain a speed-up ratio reaching up to 60 times. The executing efficiency of the Harris corner detecting parallel algorithm based on the GPU is improved obviously, and the good real-time processing capacity is shown in the aspect of large-scale data processing.

The invention provides a log processing method based on a Linux message queue. The log processing method includes the following steps that a log processing system is created; the log processing system is used for processing logs. Compared with the prior art, the log processing method based on the Linux message queue can easily and conveniently record the logs; log information generated in the process of parallel software execution is controlled and recorded more accurately so as to reflect the time and sequence of all evens generated in the operation process of parallel programs, so that in an Linux operation system, the log processing system meeting higher requirements is provide, and diversified and detailed requirements of users are met; the log processing method is high in practicability and easy to popularize.

The embodiment of the invention provides a vehicle upgrading method and device, and the method is based on a preset vehicle upgrading architecture, the preset vehicle upgrading architecture comprisesan upper computer for online upgrading, a central gateway, and a plurality of communication channels, and the plurality of communication channels are respectively connected with the upper computer through the central gateway. The method comprises the steps of enabling the upper computer to obtain a to-be-upgraded ECU list for a to-be-upgraded vehicle, wherein the to-be-upgraded ECU list comprisesa plurality of to-be-upgraded ECUs; determining a communication channel corresponding to each ECU to be upgraded according to the list of the ECUs to be upgraded; and upgrading the ECUs to be upgradedin parallel through the corresponding communication channels. The upgrading strategy of the multi-channel ECU parallel software is completed based on the multiple communication channels, the whole vehicle software upgrading speed is increased, the software upgrading success rate is increased and the vehicle power consumption is reduced by shortening the vehicle software upgrading time, and the unnecessary upgrading waiting time is shortened.

Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development.

The invention discloses a dynamic distributing method of software testing resources based on a multi-object difference evolutionary algorithm, wherein the method can be applied to modularized tests on serial / parallel software systems. Aiming at the situations that the resources are wasted due to the fact that the existing test methods do not consider the variations along with the test progress, the method comprises the following steps: S1, encoding feasible solutions; S2, dividing test stages; S3, setting control parameters; S4, initializing clusters; S5, implementing mutation operations; S6, implementing interlace operations; S7, implementing selection operations based on non-dominate ranking; S8, judging whether the maximum iteration time is reached, and jumping to step S5 if it is not; otherwise, jumping to step S9; S9, decoding pareto solutions; S10, judging whether non-implemented test stages still exist, and ending the solving process if not, or otherwise, jumping to step S11; updating testing resources for the next test stage, and jumping to step S4 for entering the next test stage.

The invention discloses a communication method suitable for monitoring MPI (Message Passing Interface) parallel software. The method comprises an MPI communication process, an MPI calculation process and host monitoring software, and the MPI communication process comprises an OpenMP command thread and a state thread. The method comprises the following steps: 1, the MPI communication process receives a command of the host monitoring software, and forwards the command to the MPI calculation process in a non-blocking way; 2, the MPI calculation process receives the command transmitted by the MPI communication process, executes the command to control a calculation task, and transmits state information to the MPI communication process regularly or in an event-driving way; 3, the MPI communication process receives the state information of the MPI calculation process, and transmits the state information to the host monitoring software. By adopting the communication method, parallel software consisting of a plurality of MPI processes can be monitored via the host monitoring software, and the aim of hardly influencing the parallel software calculation performance is fulfilled.

A method and a system for identifying and resolving conflicts between design results from a parallel software design. The method includes: receiving a design diagram, wherein the design diagram includes a plurality of nodes and arrows connecting different nodes, with each node indicating a design artifact, and an arrow directed from one node to another node indicating that a design artifact corresponds to the one node depends on a design artifact corresponding to the other node; determining a level of a design artifact in the design diagram, identifying different design artifacts at a given level of the design diagram that depend on a common design artifact, and marking them as isomorphic design artifacts; and outputting a design diagram with the isomorphic design artifacts marked. A conflict between relevant designs are automatically identified in a bottom-up approach according to a software design hierarchy to facilitate conflict resolution.

A method for allocating memory in a parallel processing computing system in which there is first provided a system memory available for parallel processing and first and second threads. The method includes using the first thread to request memory from the system memory; allocating to the first thread a first pool of memory and associating the memory pool with the second thread; using the second thread to request memory from the system memory; allocating to the second thread a second pool of memory and associating the memory pool with the first thread; using the first thread to request further memory from the second thread; and allocating to the first thread a portion of the second pool of memory from the second thread without making a request to the system memory.

The invention provides a method and system for monitoring IB network flow. The method comprises the steps: deploying a server cluster, and configuring an IB network card and a driver for nodes in thecluster; starting an IB networking service, and carrying out IB communication of the cluster server; and running parallel software on the multiple nodes, and executing the monitoring script on the to-be-tested node to obtain the occupation condition of the IB network flow. By running the parallel software on the cluster node, executing the monitoring script on the node and obtaining the real-timeflow values sent and received by the performance counting port, whether the IB network on the current node is occupied or not is judged, the defect that the use condition of the IB network cannot be obtained in the prior art is overcome, and daily maintenance of the cluster network is facilitated.

The embodiment of the invention provides a reusable code library construction method and device for a software-defined satellite, and the method comprises the steps: obtaining the project information,element information and element relation information of a to-be-stored object, wherein the element information comprises at least one of variable information, function information, data type information, class definition information, macro definition information, function declaration information and header file information, and the element relationship information comprises an element reference relationship and a source code organization relationship, wherein the to-be-stored object comprises a source code file or one or more rows of programming commands; and storing the to-be-stored object by using the obtained fine-grained information, the fine-grained information comprising element information and element relationship information. Some embodiments of the invention can facilitate incremental compilation of codes by a compiler through fine-grained element storage codes, and facilitate parallel software development of users.

The invention relates to the technical field of parallel computing, in particular to a parallel computing component and method and a corresponding parallel software development method and system. The parallel computing component comprises a parallel computing component interface, a data distribution storage unit, a data parallel communication unit and a numerical parallel computing unit, wherein the parallel computing component interface is used for providing numerical data for other units and feeding back numerical data subjected to numerical computation; the data distribution storage unit is used for storing a data field and the numerical data received from the parallel computing component interface in a private memory space of a progress; the data parallel communication unit is used for copying data fields from private memory spaces of other progresses and storing the data fields to a local progress; the numerical parallel computing unit is used for computing the numerical data of the local progress independently according to a numerical analog computation process of a numerical algorithm. By means of the method and system, the reusability, maintainability and extendibility of a software module can be improved remarkably, and the computing efficiency of application software is improved remarkably.

A method and a system for identifying and resolving conflicts between design results from a parallel software design. The method includes: receiving a design diagram, wherein the design diagram includes a plurality of nodes and arrows connecting different nodes, with each node indicating a design artifact, and an arrow directed from one node to another node indicating that a design artifact corresponds to the one node depends on a design artifact corresponding to the other node; determining a level of a design artifact in the design diagram, identifying different design artifacts at a given level of the design diagram that depend on a common design artifact, and marking them as isomorphic design artifacts; and outputting a design diagram with the isomorphic design artifacts marked. A conflict between relevant designs are automatically identified in a bottom-up approach according to a software design hierarchy to facilitate conflict resolution.

The invention provides a universal installation method for VASP software in different supercomputing clusters, which comprises the following steps: checking a hardware architecture of a supercomputingcluster, searching a CPU processor type, a version and GPU equipment, and feeding back searched hardware architecture information to a front-end user; detecting a software environment of the supercomputing cluster, searching compilers, mathematical libraries and MPI parallel software installed in the current supercomputing cluster, and recording respective installation paths of the compilers, themathematical libraries and the MPI parallel software; configuring a compiler, compiling installed MPI parallel software through the compiler, and then selecting a mathematical library according to the compiler for compiling and path adding; configuring a third-party function library and a wannier function tool through a compiler, and adding respective pre-compilation options and mathematical library paths; and compiling the VASP of the CPU version when the GPU equipment is not detected by the supercomputing cluster, and compiling the VASP of the GPU version when the GPU equipment is detectedby the supercomputing cluster.

The embodiment of the present application provides a method and device for constructing a reusable code base for a software-defined satellite. The method for constructing a reusable code base for a software-defined satellite includes: acquiring item information, element information, and element information of an object to be stored Relationship information, where the element information includes at least one of variable information, function information, data type information, class definition information, macro definition information, function declaration information, and header file information, and the element relationship information includes element references relationship and source code organization relationship, the object to be stored includes a source code file or one or more lines of programming commands; the object to be stored is stored with the obtained fine-grained information, wherein the fine-grained information includes element information and element relationship. information. Some embodiments of the present application store code by fine-grained elements, which can facilitate the compiler to incrementally compile the code, and facilitate parallel software development by the user.

The invention discloses a server group system with single system reflection, including a hardware layer, a distributed virtual machine monitor layer and an operation system layer; wherein, the hardware layer includes a plurality of nodes, a CUP of the nodes supports the hardware virtualization and the nodes are connected via a high-speed network. The distributed virtual machine monitor layer is provided with a virtual machine monitor on the hardware of each node and the virtual machine monitors of the nodes are communicated through bottom communication software and the high-speed network. Theoperation system layer supports various commercial operation systems of cc-NUMA and existing various cc-NUMA-oriented paralleling software can be operated on the system without modification. Based onthe virtualization of the hardware resources, the system achieves the single system reflection of the server group system. The server group system provided by the invention has the advantages of goodtransparency, high performance, wide application range, moderate realizing difficulty, etc.

The invention discloses a method for dynamically allocating software testing resources based on a multi-objective differential evolution algorithm, which can be applied to modular testing of serial-parallel software systems. It is aimed at the situation that the current test resource allocation method does not consider the resource waste caused by the change of the test process. The method includes steps: S1, coding for feasible decoding; S2, division of testing phases; S3, setting control parameters; S4, initializing population; S5, mutation operation; S6, crossover operation; S7, selection operation based on non-dominated sorting; S8 , to judge whether the maximum number of iterations has been reached, if not, then skip to S5; if so, then skip to S9; S9, to decode the pareto; S10, to judge whether there is still an unfinished test stage, if not, then end the solution process; If it exists, skip to S11; S11, update the test resources of the next test stage, skip to S4, and enter the next test stage.