30 results about "Block random access memory" patented technology

The present invention relates to the field of data processing, and provides a target detection hardware accelerator and an acceleration method. The accelerator includes a convolution operator integrated with a multiplier and an adder, and the convolution operator receives volumes stored in block random access memory in advance. Product weight data and feature maps, the multiplier performs multiplication operations on the convolution weight data and feature maps to obtain multiplication result data and convolution offset data, and the adder performs multiplication result data and convolution offset data The data is shifted, added and summed to obtain the multiplication and accumulation result data; the pooling operation unit is used to receive the multiplication and accumulation result data and perform a pooling operation, and output the pooling result data; the RBR operation unit is used to perform the multiplication and accumulation result data; The pooling result data is subjected to batch normalization and quantization to obtain target feature data and stored in the block random access memory. The invention can reduce the time and power consumption required by the accelerator for data transfer, and improve the working efficiency of the accelerator.

The embodiment of the invention provides an interrupt processing device and method. The interrupt processing device and method are applied to the technical field of interrupt control, can save hardware resources, and can reduce hardware cost. The interrupt processing device comprises a block random access memory, an interrupt flag bit write-in module, an interrupt flag bit output module, an interrupt flag bit read-out module and an interrupt flag bit removal module, wherein the block random access memory at least comprises m memory cell groups; the interrupt flag bit write-in module is used for writing interrupt flag bit information of any function module in the memory cell group corresponding to the function module; the interrupt flag bit output module is used for generating an interrupt event processing request and sending the interrupt event processing request to a processor; the interrupt flag bit read-out module is used for obtaining the interrupt flag bit information of the memory cell group corresponding to the function module and sending the interrupt flag bit information to the processor; the interrupt flag bit removal module is used for removing effective information corresponding to an interrupt source. The interrupt processing device is used for processing an interrupt event.

The invention provides a basic computing unit and a computing method of a convolutional neural network. The basic computing unit includes a controller, an addition tree, an input buffer, several computing units, and an output buffer; the computing unit includes a block random access memory, Several convolution operation units, internal adders, activation pooling units. Based on the control of the controller, the input buffer loads the image data of the corresponding number of lines to each calculation unit, and the block random access memory sends the effective number of lines and the initial number of lines to each convolution operation unit so that it can obtain the image data of the corresponding number of lines; The convolution operation unit processes the image data and sends it to the addition tree through the internal adder; the addition tree processes the image data sent by each internal adder and sends it to an activation pooling unit; the activation pooling unit processes the image data and sends it to the output terminal cache. The solution can realize the algorithm based on hardware, so that the completion time of the algorithm can be controlled.

The present invention provides a method and system for dynamically buffering user information, which are used for solving the problem of excessive resources for buffering user information. In the present invention, by storing a starting address of a Transport Block (TB) located in a code block parameter buffer area into a TB buffer area, and storing the starting address of each code block located in the data buffer area into the code block parameter buffer area according to the starting address of the TB located in the code block parameter buffer area, wherein the code block is segmented from the TB, a concatenation module, when a concatenation is performed, finds out the starting address of the TB located in the code block parameter buffer area from the TB buffer area according to a User Equipment (UE) index, and finds out the starting address of the code block located in the data buffer area according to a current code block index maintained by the concatenation module. Thus the waste of resources for buffering user information is decreased and more Block Random Access Memories (BRAMs) are saved.

A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory.

An embodiment of the present invention provides a data processing method and device, which acquires data information of pixels in a display device, and the data information includes compensation data and pixel positions of the pixels; and determines the compensation data of the pixels according to a preset mapping relationship In the storage location of the block random access memory, wherein the block random access memory includes multiple groups of data units stored sequentially, the order in which the data units adjacent to the storage positions are taken out is adjacent, and the data units include the data units taken out in the same clock cycle A plurality of compensation data, the plurality of compensation data are sequentially stored in the block random access memory; and the compensation data is stored in a storage space corresponding to the storage location. In this way, the compensation data can be preferentially stored in a block random access memory, the storage capacity of the block random access memory can be fully utilized, and the number of used block random access memories can be reduced, thereby reducing the cost of the FPGA.

The invention relates to a performance testing method of an FPGA embedded multiplier, comprising the following steps: (1) IP core function design of the embedded multiplier; (2) pseudo-random sequence test vector design; (3) RTL-level code simulation; ( 4) Test result analysis circuit design; (5) Module replication and output logic design. The screening test method of the FPGA embedded multiplier provided by the present invention adopts the test method based on BIST, which solves the shortcomings of high ATE test cost and difficult test technology; at the same time, the pseudo-random sequence is used as the stimulus input, which reduces the test time. Improved testing efficiency. This method makes full use of the programmable characteristics of the FPGA chip, as well as the abundant programmable logic units and embedded memory units (Block Random Access Memory, BRAM) inside the chip. The invention has simple implementation steps, strong portability and certain engineering application value.

The integrated circuit may include a programmable circuit (270) operable according to a first clock frequency, and a memory block (205). The memory block may include a storage element (210) having at least one data port and a memory processor (215) coupled to the data port of the storage element and to the programmable circuit. The memory processor may be operable according to a second clock frequency higher than the first clock frequency. Furthermore, the memory processor may be hardwired and dedicated to performing operations in the storage elements of the memory block.

The invention provides a programmable logic controller (PLC) high speed pulse counting implementation system based on a field programmable gate array (FPGA). The PLC high speed pulse counting implementation system based on the FPGA comprises the FPGA. The FPGA comprises a dual-port block random access memory (RAM), a comparison control state machine and a counter pile, wherein the dual-port block RAM comprises multiple groups of comparison registers, the counter pile comprises multiple counters which are used for counting input pulses, each counter in the counter pile corresponds to one group of comparison registers in the dual-port block RAM, and the comparison control state machine is used for reading the value of each comparison register from the dual-port block RAM in a cyclic mode and comparing the value of each comparison register with the value of one corresponding counter in the counter pile. The invention further provides a method corresponding to the PLC high speed pulse counting implementation system based on the FPGA. According to the PLC high speed pulse counting implementation system based on the FPGA and the corresponding method, comparative data are stored in the dual-port block RAM inside the FPGA, the comparison control state machine is used for comparing the comparative data in the dual-port block RAM with the values of the counters in a cyclic mode, and therefore counting and comparison of the high speed pulses through a PLC are realized.

The invention discloses a real-time paralle time-delay and phase-shift beam forming method based on a field programmable gate array (FPGA), which includes: (1) the FPGA receives half of beam forming coefficient data at an expected angle and stores the beam forming coefficient data into a connected static random access memory (SRAM); (2) the FPGA receives sample data from receipt signals of each of array elements of arrays and stores the sample data in a first Block random access memory (RAM), and also performs an alternant read-write in two groups of the first Blocks RAM; a group of corresponding beam forming coefficient data from SRAM are read and stored in a group of Q second Block RAMs of FPGA; (3) simultaneously, beam forming coefficient data of Q second Block RAMs are read, one sample datum of the first Block RAM is selected according to the time-delay amount; the two arrays of data are performed multiplication and accumulation to obtain Q beam forming results which are stored inQ latches; the results are sequentially sent out in time sharing until all beam forming results are sent out; and (4) before the sample data of next sampling moment of receipt signals of each of array elements of arrays arrive, the step (2) is repeatedly executed until the process of the beam forming of whole received sample data from receipt signals of each of array elements of arrays is finished.

The invention relates to a screening and testing method of FPGA programmable logic resources. The method comprises the following steps of 1 programmable logic resource function design, 2 lookup tabletesting input vector design, 3 RTL-level code emulation, 4 testing result analysis circuit design and 5 module copying and output logic design. According to the screening and testing method of the FPGA programmable logic resources, a testing method based on a BIST is adopted, and the defects that the ATE testing expense is high, and the testing technical difficulty is large are overcome. All LUT modules and DFF modules can be covered only through two sets of matching codes, and the testing efficiency is improved. According to the method, the programmable characteristic of an FPGA chip and richchannel resources and a block random access memory (BRAM) in the chip are fully utilized. The method is simple in implementation step and high in transportability and has certain engineering application value.

The invention provides an image brightness statistical method and an imaging device, which relate to the technical field of image processing. The method includes: obtaining the bit width of the pixel value of the image to be processed and the maximum bearable bit width of the block random access memory of the hardware device for performing brightness histogram statistics; according to the bit width of the pixel value of the image to be processed, each The pixel data is divided into multiple groups of pixel data, so that the bit width of each group of pixel data is less than or equal to the maximum acceptable bit width; according to the brightness histogram statistics of the same group of pixel data in each pixel data, the brightness corresponding to each group is obtained Histogram component: Determine the brightness evaluation value component corresponding to each group according to the brightness histogram component corresponding to each group and the pixel number of the image to be processed; determine the brightness evaluation value of the image to be processed according to each brightness evaluation value component. The present invention can conveniently perform brightness statistics for images with a high bit width to obtain brightness evaluation values.