30 results about "Block random access memory" patented technology

A video multiviewer system includes a Graphics Processing Unit (GPU) that includes a GPU memory. A video input module is operative with the GPU for receiving video data and transferring the video data to the GPU memory via a Direct Memory Access (DMA). A programmable circuit such as a Field Programmable Gate Array (FPGA) includes a multi-ported and in one aspect a dual ported block Random Access Memory (RAM) configured for a plurality of DMA channels for receiving video data and allowing uninterrupted operation of consecutive DMA transfers of video data to the GPU memory. A display displays the multiple video windows based upon video data received within the GPU memory.

An embodiment of the present invention provides a data processing method and device, which acquires data information of pixels in a display device, and the data information includes compensation data and pixel positions of the pixels; and determines the compensation data of the pixels according to a preset mapping relationship In the storage location of the block random access memory, wherein the block random access memory includes multiple groups of data units stored sequentially, the order in which the data units adjacent to the storage positions are taken out is adjacent, and the data units include the data units taken out in the same clock cycle A plurality of compensation data, the plurality of compensation data are sequentially stored in the block random access memory; and the compensation data is stored in a storage space corresponding to the storage location. In this way, the compensation data can be preferentially stored in a block random access memory, the storage capacity of the block random access memory can be fully utilized, and the number of used block random access memories can be reduced, thereby reducing the cost of the FPGA.

The invention relates to a performance testing method of an FPGA embedded multiplier, comprising the following steps: (1) IP core function design of the embedded multiplier; (2) pseudo-random sequence test vector design; (3) RTL-level code simulation; ( 4) Test result analysis circuit design; (5) Module replication and output logic design. The screening test method of the FPGA embedded multiplier provided by the present invention adopts the test method based on BIST, which solves the shortcomings of high ATE test cost and difficult test technology; at the same time, the pseudo-random sequence is used as the stimulus input, which reduces the test time. Improved testing efficiency. This method makes full use of the programmable characteristics of the FPGA chip, as well as the abundant programmable logic units and embedded memory units (Block Random Access Memory, BRAM) inside the chip. The invention has simple implementation steps, strong portability and certain engineering application value.

The integrated circuit may include a programmable circuit (270) operable according to a first clock frequency, and a memory block (205). The memory block may include a storage element (210) having at least one data port and a memory processor (215) coupled to the data port of the storage element and to the programmable circuit. The memory processor may be operable according to a second clock frequency higher than the first clock frequency. Furthermore, the memory processor may be hardwired and dedicated to performing operations in the storage elements of the memory block.

The invention discloses a real-time paralle time-delay and phase-shift beam forming method based on a field programmable gate array (FPGA), which includes: (1) the FPGA receives half of beam forming coefficient data at an expected angle and stores the beam forming coefficient data into a connected static random access memory (SRAM); (2) the FPGA receives sample data from receipt signals of each of array elements of arrays and stores the sample data in a first Block random access memory (RAM), and also performs an alternant read-write in two groups of the first Blocks RAM; a group of corresponding beam forming coefficient data from SRAM are read and stored in a group of Q second Block RAMs of FPGA; (3) simultaneously, beam forming coefficient data of Q second Block RAMs are read, one sample datum of the first Block RAM is selected according to the time-delay amount; the two arrays of data are performed multiplication and accumulation to obtain Q beam forming results which are stored inQ latches; the results are sequentially sent out in time sharing until all beam forming results are sent out; and (4) before the sample data of next sampling moment of receipt signals of each of array elements of arrays arrive, the step (2) is repeatedly executed until the process of the beam forming of whole received sample data from receipt signals of each of array elements of arrays is finished.