Target detection hardware accelerator and acceleration method

Abstract

The invention relates to the field of data processing, and provides a target detection hardware accelerator and an acceleration method, and the accelerator comprises: a convolution arithmetic unit integrated with a multiplier and an adder, wherein the convolution arithmetic unit receives convolution weight data and a feature map which are stored in a block random access memory in advance, the multiplier performs multiplication operation on the convolution weight data and the feature map to obtain multiplication result data and convolution offset data, and the adder performs shift addition summation processing on the multiplication result data and the convolution offset data to obtain multiply-accumulate result data; a pooling operation unit which is used for receiving the multiply-accumulate result data, performing pooling operation and outputting pooling result data; and a RBR operation unit which is used for performing batch standardization and quantification on the pooling result data to obtain target feature data and storing the target feature data in the block random access memory. The time and power consumption required by the accelerator for data carrying can be reduced, andthe working efficiency of the accelerator is improved.

Description

technical field [0001] The invention relates to the field of data processing, in particular to an object detection hardware accelerator and an acceleration method. Background technique [0002] With the support of big data analysis and large-scale high-speed computing platform, neural network technology has been developed sufficiently. On the one hand, neural network algorithms continue to improve. After CNN (Convolutional Neural Networks, convolutional neural network), new network models such as RNN (Recurrent Neural Network, cyclic neural network) and GAN (Generative Adversarial Networks, generative confrontation network) emerge in endlessly. ; On the other hand, due to the outstanding performance of neural network algorithms in the fields of image recognition, speech analysis and natural language processing, they are widely used in embedded systems. An embedded system is a dedicated system on a chip, which has strict requirements on system performance and power consumpti...

AI Technical Summary

Problems solved by technology

However, most of the existing neural network accelerators use DRAM to read data in the process of data transfer, which needs to be transmitted through the bus. The bandwidth of the bus is limited, and the power consumption and delay of reading a large amount of data from DRAM are very large. Greatly reduces the working efficiency of the accelerator

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