Method and device for accessing register, electronic equipment and readable medium

Abstract

The invention relates to a method and device for accessing a register, electronic equipment and a computer readable medium. The method comprises the following steps: receiving a write operation command, wherein the write operation command comprises an enable pulse signal, an address bus signal, a read-write mark signal and a write data bus signal; when the enable signal is valid, writing the writedata bus signal into a specified position of a block random access memory according to an address bus signal in the write operation command; and writing the data of the specified position on the block random access memory into a corresponding register. According to the method and device for accessing the register, the electronic equipment and the computer readable medium, screened signals of theregister can be kept stable within a certain period of time, time sequence relaxation constraint is facilitated, logic resources are saved, and cross-clock-domain read-write operation can be carried out on the register.

Description

technical field [0001] The present disclosure relates to the field of computer information processing, in particular, to a method, device, electronic equipment and computer-readable medium for accessing registers. Background technique [0002] Accessing registers is a common basic operation in the computer field, based on which the information transfer between the visitor and the visited is realized. When the interviewee is the register signal in the FPGA chip, different implementation schemes will involve engineering issues such as whether the timing can be achieved better, how much logic resources are consumed, and so on. [0003] When implementing register read and write access based on FPGA, due to the unreasonable design scheme, the timing of the FPGA project will be too poor, which will affect the project quality, cause functional hidden dangers, and also cause a waste of logic resources. Therefore, designing an engineering solution that saves logic resources and has ...

AI Technical Summary

Problems solved by technology

[0003] When implementing register read and write access based on FPGA, due to the unreasonable design scheme, the timing of the FPGA project will be too poor, which will affect the project quality, cause functional hidden dangers, and also cause waste of logic resources.

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