32results about How to "Sufficient phase margin" patented technology

An operational amplifier includes an input stage amplifier that receives an input signal, an output stage amplifier that amplifies a signal output from the input stage amplifier and outputs the signal, a capacitor that is connected between an input node and an output node of the output stage amplifier, and a charge and discharge control circuit that controls a charge and discharge current of the capacitor.

In a multi-phase power converter using a phase-locked loop (PLL) arrangement for interleaving of pulse frequency modulated (PFM) pulses of the respective phases, improved transient response, improved stability of high bandwidth output voltage feedback loop, guaranteed stability of the PLL loop and avoidance of jittering and phase cancellation issues are achieved by anchoring the bandwidth at the frequency of peak phase margin. This methodology is applicable to multi-phase power conveners of any number of phases and any known or foreseeable topology for individual phases and is not only applicable to power converters operating under constant on-time control, but is extendable to ramp pulse modulation (RPM) control and hysteresis control. Interleaving of pulses from all phases is simplified through use of phase managers with a reduced number of PLLS using hybrid interleaving arrangements that do not exhibit jittering even when ripple is completely canceled.

The invention relates to a fully integrated load pole compensation linear voltage stabilizer, which includes two parts: a main circuit of the linear voltage stabilizer and a load pole compensation circuit. The main circuit of the linear regulator is responsible for providing a stable DC output voltage and suppressing low-frequency disturbances of the output voltage. The load pole compensation circuit monitors the high-frequency disturbance of the output voltage, and stabilizes the output voltage by quickly injecting compensation current, which is equivalent to introducing a low impedance at the load end to reduce the RC constant at this point, ensuring that the output end is still constant under light load conditions. The second pole and away from the unity-gain bandwidth guarantees the phase margin of the feedback loop.

A method for adaptively improving the stability of an LCL grid-connected inserter system under the condition of a weak grid comprises the following steps: adding a lead correction link to the LCL grid-connected inserter system, and pre-configuring the parameters of the lead correction link; measuring the inductive impedance (Lg) of the grid through a small signal injection method; judging whether there is a need to set the parameters of the lead correction link; if there is no need to set the parameters of the lead correction link, ending the process; and if there is a need to set the parameters of the lead correction link, setting the indexing coefficient (a) and the time constant (T) of a lead network in the lead correction link, and setting the adjustment coefficient (ka) of the lead correction link. According to the invention, the lead correction link is added to the LCL grid-connected inserter system, the impedance of the grid is measured through the small signal injection method, and the parameters of the lead correction link are set to make compensation for the system phase when the phase angle margin of the system is insufficient. By adaptively adjusting the parameters of the lead correction link to make compensation for the phase margin of the system according to the result of grid impedance measurement, enough stable margin can be kept for the system, and safe and stable operation of the system can be ensured.

A control circuit of a power supply that generates an output voltage from an input voltage includes a gain adjustment circuit that adjusts a gain of an alternating-current component of the output voltage. An addition circuit adds an output signal of the gain adjustment circuit to a first feedback voltage, which is in accordance with the output voltage, to generate a second feedback voltage. A voltage generation circuit generates a comparison reference voltage that changes at a given rate with respect to a first reference voltage that is set according to a target value of the output voltage. A switch control circuit controls the output voltage by switching a switch circuit, to which the input voltage is supplied, at a timing according to a result of a comparison of the second feedback voltage with the comparison reference voltage.

A power supply design method based on frequency domain analysis, which includes the following steps: the first step is to evaluate the test platform, measure the open-loop transfer function of the test platform, and determine the design target; the second step is to load the test target, according to Test the parameters to obtain the compensation parameters, and draw the Bode diagram of the compensation parameters; then superimpose the Bode diagram of the compensation parameters and the Bode diagram of the open-loop transfer function to obtain a closed-loop curve; the third step is to adjust the parameters of the error amplifier, select parameter value, and the selected parameter value is debugged in the circuit board of the specific application, and the Bode diagram response curve of the whole loop is obtained; the fourth step is to confirm the test result, and obtain the closed-loop result on the test platform. Bode diagram, comparing the closed-loop Bode diagram on the test platform with the computer simulation diagram to confirm whether the two match. The invention greatly reduces the design period, improves the quality of products, and improves the research and development efficiency.

The invention relates to a self-adaption zero-frequency compensation circuit in a low-voltage difference linear voltage regulator. The output end of a transconductance amplifier is connected with a voltage regulation pipe by a voltage bumper, a current detection circuit is connected with the voltage bumper and the common end of the voltage regulation pipe, and the other end is connected with a variable-resistance circuit connected with the compensation end of the transconductance amplifier. In the invention, when a load is higher and current is lower, the current detection circuit can detect the load and the current and the load and the current act on the variable-resistance circuit at the moment to ensure that the resistance is enlarged, and the zero position is also relatively lower; on the contrary, when the load is reduced and the current is enlarged, the resistance value of the variable-resistance circuit is reduced, and the zero position is higher. Therefore, the self-adaption zero can change along with the change of a pole so that the compensation circuit takes the effect of compensation and effectively ensures the stable state of system operation. The compensation circuit successfully solves the problem of poor stability of a low-voltage difference linear voltage regulator so that a load capacitance equivalent series resistance is not really important to the influence on system stability, transient response and ripple waves.

The invention provides a control device of a power factor correcting circuit and a control method. The power factor correcting circuit (200) is driven by the input of an input circuit (100), the control device comprises a sampling circuit (300), a driving circuit (400) and a control circuit (500), wherein the control circuit (500) comprises a processing unit (510), the sampling circuit (300) acquires the status signal of the power factor correcting circuit (200), and sends the signal to the processing unit (510), the processing unit (510) controls the output parameters of the control circuit (500) according to the status signal so as to control the driving circuit (400), and the driving circuit (400) outputs corresponding driving signals so as to control the power factor correcting circuit (200). The invention has the advantage that the control has sufficient phase margin, wide gain bandwidth and high gain.

The invention provides a low-drop-out voltagestabilizer. The low-drop-out voltagestabilizer comprises an error amplifier, a second field effect tube, a power device, a first field effect tube and a super source follower, wherein the positive electrode input end of the error amplifier receives reference voltage, and the negative electrode input end is connected with the output end, the drain electrode of the second field effect tube is connected with the output end of the error amplifier, the source electrode of the second field effect tube is grounded through a second current source, and the grid electrode of the second field effect tube is grounded through a second current source; the drain electrode of the power device is connected to the power voltage, the drain electrode of the power device is connected with the drain electrode of the first field effect tube, and meanwhile, the power device is grounded through a first capacitor, grounded through a load current source and grounded through a third capacitor and a first current source; the grid electrode of the first field effect tube is connected with the grid electrode of the second field effect tube, the drain electrode of thefirst field effect tube is connected with the source electrode of the power device, and the source electrode of the first field effect tube is grounded through the first current source and meanwhile connected with the input end of the super source follower; the output end of the super source follower is connected with the grid electrode of the power device and meanwhile grounded through a second capacitor.

The invention discloses a gain enhanced full-differential amplifier structure for a pipeline ADC. The structure comprises an MDAC (Multiplying Digital to Analog Converter) master amplifier and two secondary amplifiers. The master amplifier is a telescopic cascode structure. Two PMOS transistors form output impedance Rp of the cascode structure. Two NMOS transistor form the output impedance Rn of the cascode structure. The two secondary amplifiers of an operational amplifier AMP1 and the operational amplifier AMP2 are used for improving the Rp and the Rn. The two secondary amplifiers comprise output voltage stabilizing structures which are used for ensuring the gate voltage stability of the common gate PMOS transistors and the common gate NMOS transistors in the operational amplifier of the full-differential master amplifier. The operational amplifier AMP1 is a two-level operational amplifier. A current input mode is taken as an input mode of a second-level amplifier. The load of a first level-amplifier is reduced. The bandwidth and gain are increased. The gain of the master amplifier is increased from original Gm1*(Rp||Rn)*A2 to Gm1*(AP*Rp||AN*Rn)*A2.