34results about How to "Solve the speed bottleneck" patented technology

The invention provides an FPGA based IPv6 data packet high-speed processing device and an operational method thereof, and belongs to the technical field of transceiving processing of the data packet. The device comprises a microprocessor interface module, an IPv6 data packet encapsulating transmission module, an IPv6 data packet decapsulation analysis module, an Ethernet MAC controller module, anSRAM controller module and a user interactive module, wherein the microprocessor interface module is connected with an external microprocessor, the IPv6 data packet encapsulating transmission module,the IPv6 data packet decapsulation analysis module, the SRAM controller module and the user interactive module respectively; and the IPv6 data packet encapsulating transmission module and the IPv6 data packet decapsulation analysis module are connected with the Ethernet MAC controller module respectively. The device has the advantages that: the IPv6 is fully supported, the speed of processing thenetwork data is greatly improved, the modularization design is adopted, and various microprocessors or bus interfaces are adapted only by modifying the microprocessor interface module, so that the device is high in expansibility, versatility and flexibility.

The invention discloses a design method of an LDPC (Low-Density Parity-Check Code) decoder compatible with a DVB-S2X standard, which mainly solves the problem of long iteration time of a decoder in an existing system. The design method of the LDPC decoder compatible with the DVB-S2X standard comprises the implementing steps of 1, designing a data buffer, converting input single-path data into 360-path parallel data after the input single-path data are subjected to sequence adjustment, buffering the 360-path parallel data and carrying out decoding initiation for the data; 2, designing a first barrel-shaped shifting module, shifting the 360-path data after variable node updating and carrying out check node updating; 3, designing a second barrel-shaped shifting module, and shifting the 360-path data after the check node updating is finished and then carrying out variable node updating; 4, after the number of decoding iterations reaches to the set maximum number of iterations, calculating hard decision information for the 360-path data; and 5, after the hard decision information is subjected to the decoding decision, outputting the hard decision information in sequence so as to finish the decoding. According to the design method of the LDPC decoder compatible with the DVB-S2X standard, the iteration time of the LDPC decoder is reduced, and the throughput of the decoder is increased by one time.