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FPGA based IPv6 data packet high-speed processing device and operational method thereof

A high-speed processing and data packet technology, applied in data exchange networks, digital transmission systems, electrical components, etc., to solve problems such as processing speed discounts

Inactive Publication Date: 2011-04-20
SHANDONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method has relatively good flexibility, compared with pure hardware, its processing speed will be greatly reduced

Method used

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  • FPGA based IPv6 data packet high-speed processing device and operational method thereof
  • FPGA based IPv6 data packet high-speed processing device and operational method thereof
  • FPGA based IPv6 data packet high-speed processing device and operational method thereof

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Experimental program
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Embodiment 1

[0038] Embodiment 1: (device embodiment)

[0039] Embodiments of the device of the present invention are Figure 1-2 As shown, it includes a microprocessor interface module 1, an IPv6 packet encapsulation sending module 2, an IPv6 packet unpacking analysis module 3, an Ethernet MAC controller module 4, a SRAM controller module 5 and a user interaction module 6, and is characterized in that The microprocessor interface module 1 is connected with the external microprocessor 15, the IPv6 data packet encapsulation sending module 2, the IPv6 data packet unpacking analysis module 3, the SRAM controller module 5 and the user interaction module 6 respectively, and sends the external microprocessor 15 The address, data and control signals of the system are synchronized and converted into internal control signals and configuration information, requesting the IPv6 data packet encapsulation and sending module 2 to perform preprocessing and sending operations, and receiving the request sig...

Embodiment 2

[0045] Embodiment 2: (method embodiment)

[0046] The operating method of the microprocessor interface module in the device of the present invention is as image 3 As shown, the steps are as follows:

[0047] 19. start;

[0048] 20. Receive instructions from the microprocessor;

[0049] 21. Receive a write register instruction from the microprocessor, if so, go to step 25; otherwise go to the next step;

[0050] 22. Receive the read register instruction from the microprocessor, if so, go to step 26; otherwise go to the next step;

[0051] 23. Receive a request to send an instruction from the microprocessor, if so, go to step 27; otherwise go to the next step;

[0052] 24. Receive the receiving completion signal from the IPv6 packet unpacking analysis module, if so, go to step 28; otherwise go to step 20;

[0053] 25. Write the data sent by the processor data bus into the register of the corresponding module, complete the configuration process, and then turn to step 20;

...

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Abstract

The invention provides an FPGA based IPv6 data packet high-speed processing device and an operational method thereof, and belongs to the technical field of transceiving processing of the data packet. The device comprises a microprocessor interface module, an IPv6 data packet encapsulating transmission module, an IPv6 data packet decapsulation analysis module, an Ethernet MAC controller module, anSRAM controller module and a user interactive module, wherein the microprocessor interface module is connected with an external microprocessor, the IPv6 data packet encapsulating transmission module,the IPv6 data packet decapsulation analysis module, the SRAM controller module and the user interactive module respectively; and the IPv6 data packet encapsulating transmission module and the IPv6 data packet decapsulation analysis module are connected with the Ethernet MAC controller module respectively. The device has the advantages that: the IPv6 is fully supported, the speed of processing thenetwork data is greatly improved, the modularization design is adopted, and various microprocessors or bus interfaces are adapted only by modifying the microprocessor interface module, so that the device is high in expansibility, versatility and flexibility.

Description

(1) Technical field [0001] An FPGA-based high-speed processing device and operation method for IPv6 data packets belong to the technical field of data packet sending and receiving processing. (2) Background technology [0002] High-end routers are the core equipment for Internet backbone network construction, and are operable carrier-class routers with key attributes such as high reliability, high scalability, and high performance. Because it can effectively expand the original bandwidth of the Internet backbone network, eliminate the bandwidth bottleneck of network nodes, and solve the increasing traffic pressure on the Internet backbone network, the new generation of high-end routers is gradually expanding its application occasions, except for the traditional application fields of high-end routers such as Internet backbone networks. , High-end router applications are penetrating into operators' metropolitan area networks, industry private networks, enterprise networks, cam...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/56H04L29/06H04L47/43
Inventor 刘志军马成海王运哲
Owner SHANDONG UNIV
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