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Design method of LDPC (Low-Density Parity-Check Code) decoder compatible with DVB-S2X standard

A technology of DVB-S2X and design method, which is applied in the direction of error detection coding, coding, code conversion and other directions of applying multi-bit parity bits, and can solve the problems of limiting decoder throughput and incompatibility

Active Publication Date: 2016-06-15
XIDIAN UNIV
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

In the design method of the above LDPC decoder, since only one barrel shift module is used, check node update and variable node update need to be performed alternately, which limits the throughput of the decoder; and because the DVB-S2X standard was released in 2014 Released in 2011, the above LDPC decoder is not compatible with DVB-S2X standard

Method used

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  • Design method of LDPC (Low-Density Parity-Check Code) decoder compatible with DVB-S2X standard

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Embodiment Construction

[0034] The technical method of the present invention will be further described below through the accompanying drawings and embodiments.

[0035] refer to figure 1 , the implementation steps of the present invention are as follows:

[0036] Step 1: Design the LLR cache module, adjust the order of the input log-likelihood ratio information, perform serial-to-parallel conversion and cache.

[0037] The LLR cache module includes a logarithmic likelihood ratio adjuster, a serial-to-parallel converter and a cache;

[0038] 1.1) Design a logarithmic likelihood information adjuster, use this adjuster to adjust the logarithmic likelihood ratio information of the LDPC code input decoder in order according to the following rules:

[0039] The log-likelihood ratio information of the input k information bits is directly output sequentially without sequence adjustment;

[0040] Sequentially adjust the log-likelihood ratio information of the input n-k check digits, where n is the code len...

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Abstract

The invention discloses a design method of an LDPC (Low-Density Parity-Check Code) decoder compatible with a DVB-S2X standard, which mainly solves the problem of long iteration time of a decoder in an existing system. The design method of the LDPC decoder compatible with the DVB-S2X standard comprises the implementing steps of 1, designing a data buffer, converting input single-path data into 360-path parallel data after the input single-path data are subjected to sequence adjustment, buffering the 360-path parallel data and carrying out decoding initiation for the data; 2, designing a first barrel-shaped shifting module, shifting the 360-path data after variable node updating and carrying out check node updating; 3, designing a second barrel-shaped shifting module, and shifting the 360-path data after the check node updating is finished and then carrying out variable node updating; 4, after the number of decoding iterations reaches to the set maximum number of iterations, calculating hard decision information for the 360-path data; and 5, after the hard decision information is subjected to the decoding decision, outputting the hard decision information in sequence so as to finish the decoding. According to the design method of the LDPC decoder compatible with the DVB-S2X standard, the iteration time of the LDPC decoder is reduced, and the throughput of the decoder is increased by one time.

Description

technical field [0001] The invention belongs to the field of wireless communication, and relates to a design method of an LDPC decoder compatible with the DVB-S2X standard, which can be used for decoding LDPC codes of all code lengths and code rates in the DVB-S2 and DVB-S2X standards. Background technique [0002] Low Density Parity Check Code (LDPC code) is a kind of linear block code. Many research results show that LDPC codes have good performance and are more suitable for the effectiveness and reliability of data transmission in future communication systems. Therefore, more and more communication standards use LDPC codes as their channel coding schemes. Both DVB-S2 and DVB-S2X standards have adopted LDPC codes, and the high-speed FPGA implementation of LDPC code decoders for these standards has attracted a lot of attention. Since there is only one check node update unit and variable node update unit in the LDPC decoder with a serial structure, check node update and var...

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1108
Inventor 宫丰奎安宁张南王勇秦利卿
Owner XIDIAN UNIV
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