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High-speed dual mode 16/17 pre-divider

A prescaler, high-speed technology, applied in the direction of pulse counters, counting chain pulse counters, electrical components, etc., can solve the problems of large delay, limiting frequency division frequency of dual-mode prescaler, etc., to reduce delay and solve speed Bottlenecks, effects of eliminating influence

Inactive Publication Date: 2007-09-19
SOUTHEAST UNIV
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  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

However, in this prescaler circuit, the delay caused by the feedback is still very large relative to the delay of the flip-flop itself. Improvement of the frequency division frequency of the frequency divider

Method used

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  • High-speed dual mode 16/17 pre-divider
  • High-speed dual mode 16/17 pre-divider
  • High-speed dual mode 16/17 pre-divider

Examples

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Embodiment Construction

[0013] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0014] See Figure 1 and Figure 2. The improved prescaler circuit in the prior art contains five positive-edge flip-flops, a two-input NAND gate, a two-input OR gate and a three-input OR gate, and it adopts three-input OR gate feedback control to realize 17 Frequency division, 17 frequency division when MCOUT is low level, through the state transition truth table and the timing around the pulse swallow signal shown in Figure 2, in order to make Q 2 Properly generate swallow pulse signal, Q 4 Q 3 The state only needs to change from 01 to 00, that is, the delay of the asynchronous frequency divider in the feedback process only includes Q 3 This reduces the minimum period of the input clock, thereby increasing the maximum operating frequency of the prescaler when dividing by 17. However, in the improved prescaler, the delay caused by ...

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PUM

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Abstract

Provided is a high speed two-mode16 / 17 prescaler circuit belonging to high speed frequency synthesizer and high frequency transceiver technology field. The prescaler circuit comprises three positive edge triggers, a two input or a door, a two input or a non-door, a three input and a non-door and two negative edge triggers. The synchronization frequency division unit composed by the three positive edge trigger, the two input or door and the two input and the non-door adopts rising edge trigger except 4 / 5. The asynchronization frequency division unit composed by the two negative edge triggers adopts fall edge trigger except 4. The feedback control unit adopts the three input and the non-door. The prescaler circuit prevents the influence of the feedback path to the speed of the prescale in 17 frequency division in the existing technology and reduces the delay of the feedback path thus preventing the influence of the feedback state to the synchronization 4 / 5 frequency division speed, increasing the speed of the prescaler, solving the bottleneck problem of speed of the frequency synthesizer and realizing well the 16 / 17 high frequency division of the prescaler.

Description

technical field [0001] The invention relates to a high-speed dual-mode 16 / 17 prescaler, which belongs to the technical field of high-speed frequency synthesizers and high-frequency transceivers. Background technique [0002] In the high-frequency receiving / transmitting system, the phase-locked loop frequency synthesizer is the core module in the tunable radio frequency chip. As a local oscillator source, it should generate frequency-adjustable local oscillator signal output at a certain frequency interval according to the requirements of the receiving and transmitting channels. The programmable frequency divider in the frequency synthesizer realizes the programmable output of the local oscillator frequency, in which the prescaler circuit directly receives the output signal of the voltage-controlled oscillator and works at the highest frequency, which affects the phase-locked loop frequency synthesizer speed critical circuits. In the traditional dual-mode prescaler circuit ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K23/64
Inventor 吴建辉陈作添戴学强李红张萌茆邦琴
Owner SOUTHEAST UNIV
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