67results about How to "Short channel length" patented technology

The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.

A process for producing high performance organic thin film transistors in which the molecules in the organic thin film are highly ordered and oriented to maximize the mobility of current charge carriers. The uniform monolayer surface over various substrate materials so formed, result in a more reproducible and readily manufacturable process for higher performance organic field effect transistors that can be used to create large area circuits using a range of materials.

A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

A semiconductor device includes: a semiconductor substrate having a substrate surface; a spiral body constituted by a linear semiconductor layer on which a body region including a channel region, a first source / drain region disposed on the body region, and a second source / drain region disposed under the body region or in the semiconductor substrate around the linear semiconductor layer are formed, the linear semiconductor layer being formed on the substrate surface substantially in a spiral form viewed from the substrate surface in a plan view, formed substantially in a protrudent form in a cross-sectional view, and having a pair of sidewall portions; a gate insulating film formed on at least the pair of sidewall portions constituting the linear semiconductor layer; and a gate electrode that is adjacent to the pair of sidewall portions via the gate insulating film.

The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.

The invention provides a method for preparing a catalyst used for methanol / dimethyl ether high selectivity propylene preparation, and specifically provides a method for preparing nanometer layer structured ZSM-5 molecular sieve by employing an asymmetric gemini quaternary ammonium surfactant as a template. The method comprises specific steps as follows: (1) preparing solution A by adding the template to a mixed solution comprising water and ethanol, and preparing solution B by adding aluminum sources to sulfur solution; (2) slowly adding the B solution to the A solution, uniformly stirring the mixed solution comprising the A solution and the B solution, and then adding the aluminum sources to form initial gel; and (3) moving the gel to a crystallization kettle for crystallization under 100-200 DEG C for 1-10 days. A ZSM-5 molecular sieve prepared according to the invention is in a nanometer layer structure with the thickness being 20-100 nm, the silica-alumina ratio of the molecular sieve can be adjusted, and the specific surface area and the pore volume of the molecular sieve are quite large. In a methanol / dimethyl ether high selectivity propylene preparation reaction, the propylene selectivity and P / E ratio of the nanometer layer structured ZSM-5 molecular sieve are higher than that of a conventional ZSM-5 molecular sieve, and the service lifetime of the catalyst is longer.

A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

A thin-film transistor includes a substrate (10), a gate electrode (20) provided on a portion of the substrate, an insulation layer (30) arranged to cover the gate electrode and the substrate, a source or drain (40) provided on the insulation layer in a region corresponding to a region of the gate electrode, a semiconductor layer (50) arranged to cover the source or drain (40) and the insulation layer, a drain or source (60) provided on the semiconductor in a portion of a region corresponding to a region of the source or drain (40) that overlaps with the gate electrode, and a channel (70) formed between the source or drain (40) and the drain or source (60) and having a length defined by a film thickness of the semiconductor layer (50).

The present disclosure relates to a thin film transistor substrate having a bi-layer oxide semiconductor. The present disclosure provides a thin film transistor substrate comprising: a substrate; and an oxide semiconductor layer on the substrate, wherein the oxide semiconductor layer includes: a first oxide semiconductor layer having indium, gallium and zinc; and a second oxide semiconductor layer stacked on the first oxide semiconductor layer having the indium, gallium and zinc, wherein any one layer of the first and the second oxide semiconductor layers has a first composition ratio of the indium, gallium and zinc of 1:1:1; and wherein other layer has a second composition ratio of the indium, gallium and zinc in which the indium ratio is higher than the zinc ratio.

The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost reduction and throughput improvement are possible due to the small number of steps and reduction of materials and which has a semiconductor element with a minute structure, and further a manufacturing method thereof. According to the present invention, a composition including metal particles and organic resin is irradiated with laser light and a part of the metal particles is baked to form a conductive layer typified by a wiring, an electrode or the like over a substrate. Further, a semiconductor device having the baked conductive layer as a wiring or an electrode is formed.

A semiconductor device having a structure which enables sufficient reduction in parasitic capacitance is provided. In addition, the operation speed of thin film transistors in a driver circuit is improved. In a bottom-gate thin film transistor in which an oxide insulating layer is in contact with a channel formation region in an oxide semiconductor layer, a source electrode layer and a drain electrode layer are formed in such a manner that they do not overlap with a gate electrode layer. Thus, the distance between the gate electrode layer and the source electrode layer and between the gate electrode layer and the drain electrode layer are increased; accordingly, parasitic capacitance can be reduced.

A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line.

A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.

An embodiment is a manufacturing method of a semiconductor device including the steps of forming a first insulating film; forming a first mask over the first insulating film; performing a slimming process on the first mask to form a second mask; performing an etching process on the first insulating film using the second mask to form a second insulating film; forming a first conductive film covering the second insulating film; performing a polishing process on the first conductive film and the second insulating film to form a third insulating film, a source electrode, and a drain electrode having equal thicknesses; forming an oxide semiconductor film over the third insulating film, the source electrode, and the drain electrode; forming a gate insulating film over the oxide semiconductor film; and forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.

The invention provides a method for transferring heat by conduction to the internal heat acceptor of an external combustion engine. Fuel and air are introduced and mixed to form an air / fuel mixture. The air / fuel mixture is directed into a catalytic reactor that is positioned substantially adjacent to the heater head. Heat is transferred via conduction from the catalytic reactor to the heater head and the catalytic reaction products are exhausted.