The invention discloses an FPGA intra-IO sheet interconnecting digital circuit based on re-encryption algorithm. The FPGA intra-IO sheet interconnecting digital circuit comprises a sending end digital circuit, a receiving end digital circuit and a clock generation module, wherein the sending end digital circuit comprises a plaintext data generation logic, a first asynchronous FIFO, a head synchronous LFSR encryption module, a second asynchronous FIFO, an AES encryption module, a parallel-serial conversion module, a serializer and an OBUFDS module, and the receiving end digital circuit comprises a deseriallizer, an IBUFGDS module, a serial-parallel conversion module, a third asynchronous FIFO write control logic, a third asynchronous FIFO, an AES decryption module, a fourth asynchronous FIFO, a head synchronous LFSR decryption module and a plaintext data reception logic. Encryption and decryption of interconnected data transmission processes between FPGA virtual IO sheets are realized through stable and effective re-encryption algorithm.