50results about How to "Reduce capacitive coupling effects" patented technology

A display device and a method of applying the same are introduced herein. A shielding layer is utilized to interpose between a transparent conductive layer of a touch element and a common electrode layer of a liquid crystal display (LCD) panel. With controlling variances of a first and a second control signals, a coupling current between the transparent conductive layer and common electrode layer can approach none, whereby influences of capacitive coupling effect between the common electrode layer or shielding layer and the transparent conductive layer of the touch element can be reduced. Thus, high touch accuracy of the touch element can be achieved and the noise can be eliminated simultaneously.

The invention discloses a display panel and a display device. A substrate of the display panel includes a device setting area, a first non-display area, a display area and a second non-display area, wherein the first non-display area surrounds the device setting area, and the display area surrounds the first non-display area; a plurality of data lines formed on the substrate; and a first metal layer, a second metal layer and a third metal layer formed on the substrate, all data lines include first trace parts which are located in the second metal layer; part of the data lines passing through the first non-display area also include first jumper parts, all of which are located in the third metal layer; or all first jumper parts are located in the first metal layer; or part of the first jumper parts are located in the third metal layer and other first jumper parts are located in the first metal layer. The display panel has the advantage that devices of large sizes can be normally installed and used when ensuring relatively high display panel screen ratio.

A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

The invention provides a semiconductor device, which comprises a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer. The dielectric constant of the first gate spacer is smaller than the dielectric constant of the second gate spacer. The dielectric constant of gate spacers, that is the capacitive coupling between the LDD regions and the gate, is reduced.

The invention discloses a grid driving circuit. In a display stage, in response to a low potential of a second voltage end, first and second control modules disconnect a third voltage end from a first output end; in a touch control stage, in response to a high potential of the second voltage end, the first and second control modules connect the third voltage end with the first output end; and thus, each scanning unit is provided with the first and second control modules, in the touch control stage, the first control module keeps the first output end in the low potential and the second control module keeps a second output end in the low potential, so that a capacitive coupling effect between grid lines and touch control electrodes in a touch control display panel used by the grid driving circuit is weakened, the precision of touch control detection is improved, added lines are short and narrow, an occupied frame is small in the area, and a narrow frame can be realized.

According to the embodiment, the invention discloses a gate drive circuit. In the gate drive circuit, first control modules respond to signals of first signal en and second signal ends, and in a touch control stage, third voltage ends and first output ends are conducted by virtue of the first control modules; second control modules respond to the signals of the first signal ends and the second signal ends, and in the touch control stage, the third voltage ends and the second output ends are conducted by virtue of the second control modules; therefore, by arranging the first and the second control modules in various canning units, in the touch control stage, the first output ends are controlled at a low potential by virtue of the first control modules, and meanwhile, the second output ends are controlled at a low potential by virtue of the second control modules, so that a capacity coupling action between various gate lines and a touch control electrode in a touch control display panel applied to the gate drive circuit is weakened, and touch control detection precision is enhanced; and an added cable is relatively short, relatively narrow and relatively small in occupied bezel area; therefore, the gate drive circuit is conducive to implementation of a narrow bezel.

A display device. The display device has a display panel and a drive circuit. The display panel has a pixel array formed by a plurality of pixel electrodes. The drive circuit has a plurality of data lines to drive the pixel electrodes of the pixel array. The pixel electrode of the (N-1)th row in the pixel array of the Mth column and the data line driving the pixel electrode of the Nth row have a first distance D1, the pixel electrodes of the (N+1)th row in the pixel array of the Mth column and the data line driving the pixel electrodes of the Nth row have a second distance D2, and the first distance D1 is larger than the second distance D2.

The invention provides a film transistor panel structure and a manufacturing method thereof. The structure comprises a first metallic layer as a scan line, a first passivation layer on the first metallic layer, an organic film on the first passivation layer, a second passivation layer on the organic film, through holes passing through the first passivation layer, the organic film and the second passivation layer, a second metallic layer which contacts with the first metallic layer through the through holes and serves as a grid electrode, a third passivation layer covering the grid electrode, a semiconductor active layer on the third passivation layer, and a third metallic layer which serves as a data line, a source electrode, a drain electrode and a pixel electrode. The distance between the two poles of a flat parasitic capacitor and a parallel parasitic capacitor in pixels can be increased, the parasitic capacitance is reduced, pixel noise is also reduced, and the pixel performance is improved.

The invention relates to a manufacturing method of a semiconductor memory. The manufacturing method comprises the steps of forming a plurality of bit line structures on a semiconductor substrate, extending the bit line structures in the first direction, and repeatedly arranging thebit line structures in the second direction; forming a barrier layer on the semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures; forming a sacrificial material layer filling the grooves between the bit line structures; forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along a second direction; forming a first protection isolator on the side wall of the sacrificial isolator, wherein the first protection isolator and the bit line structure define a capacitor contact window together; and removing the sacrificial spacers, forming an air gap between the two first protection spacers corresponding to the same sacrificial spacer, and forming a sealing layer at the top of the air gap.