50results about How to "Reduce capacitive coupling effects" patented technology

A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

The invention provides a touch display device and a touch display. The touch display device comprises a touch electrode and a backlight module opposite to the touch electrode. The backlight module comprises a backlight film material and a backlight iron frame for supporting the backlight film material. The backlight film material is arranged between the touch electrode and the backlight iron frame. The touch control electrodes and the backlight iron frame are electrically connected with a touch control signal end together. The touch control signal end is used for transmitting touch control signals to the touch control electrodes and the backlight iron frame. The touch electrodes and the backlight iron frame receive the same touch signals, so that the capacitive coupling effect between thetouch electrodes and the touch iron frame is eliminated. The touch sensitivity is improved. The vibration noise of the backlight film material is eliminated. The touch display provided by the invention comprises the touch display device, so that the touch display has the advantages of the touch display device.

The invention discloses a TFT (Thin Film Transistor) and a display device, belongs to the technical field of display and can reduce stray capacitance between a first metal layer and a second metal layer and increase the display quality of an LCD (Liquid Crystal Display). The TFT comprises a grid electrode, a grid electrode insulation layer, a semiconductor layer, a source electrode and a drain electrode, wherein the grid electrode insulation layer covers the grid electrode; the semiconductor layer is formed on the grid electrode insulation layer; the source electrode and the drain electrode are formed on the semiconductor layer; the semiconductor layer is provided with an extension part; a planar projection of the extension part exceeds the edge of the grid electrode, and the drain electrode covers the extension part. The TFT disclosed by the invention can be applied to high-PPI (Pixel Per Inch) display devices such as a mobile phone and a tablet computer.

The present invention discloses a thin film transistor array substrate comprising a plurality of thin film transistors, with each one thereof including a gate electrode, a gate insulation layer, an amorphous-oxide semiconductor layer and a pair of a source electrode and a drain electrode. The amorphous-oxide semiconductor layer comprises an amorphous-oxide semiconductor material having a-IGZO. The thin film transistor array substrate further comprises a first insulation layer and a second insulation layer disposed on the thin film transistors. Since the a-IGZO semiconductor layer and the thick insulation layer covered thereon are used in the present invention, a common electrode can overlap the scan lines or data lines to increase the aperture ratio of the pixel structure. Furthermore, the thick insulation layer can be fabricated through a coating process, so as to keep the a-IGZO semiconductor layer from damages during the fabrication processes.

A thin film transistor is provided. The thin film transistor includes a substrate, a gate, a gate insulating layer, a source and a drain, a channel layer, and first and second patterned passivation layers. The gate is disposed on the substrate. The gate insulating layer is disposed on the gate. The source and the drain are disposed on the gate insulating layer. The channel layer is disposed above or under the source and the drain, wherein a portion of the channel layer is exposed between the source and the drain. The first patterned passivation layer is disposed on the portion of the channel layer, wherein the first patterned passivation layer includes metal oxide, and the first patterned passivation layer has a thickness ranging from 50 angstroms to 300 angstroms. The second patterned passivation layer covers the first patterned passivation layer, the gate insulating layer, and the source and the drain.

A multi-domain liquid crystal display includes a first and a second transparent substrates, a liquid crystal layer interposed between them, a common electrode, a first and a second metal layers, a first and a second dielectric layer, multiple pixel electrodes and multiple auxiliary electrodes. The second metal layer is formed on the first dielectric layer, and the second dielectric layer is formed on the first dielectric layer and covers the second metal layer. The pixel electrodes are formed on the second dielectric layer, each of the pixel electrodes having at least one opening to divide itself into a plurality of sections. The auxiliary electrodes are formed on the second dielectric layer, and each of the auxiliary electrodes extends into the opening of the pixel electrode. The second metal layer is hollowed out at a position overlapping the auxiliary electrode to form at least one opening.

An E-paper display device including an E-paper display panel and a display driver is provided. The E-paper display panel displays an image. The image includes a first frame and a second frame. The display driver is coupled to the E-paper display panel. The display driver drives the E-paper display panel to display the image. The display driver drives a first pixel group of the E-paper display panel in a first polarity and drives a second pixel group of the E-paper display panel in a second polarity to display the first frame during a first frame period. The first pixel group and the second pixel group are arranged in interlacing. The display driver drives the second pixel group of the E-paper display panel in the first polarity to display the second frame during a second frame period. Moreover, a method for driving an E-paper display panel is also provided.

A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

The invention discloses an inductive coupling plasma coil which comprises two groups of radio-frequency coils formed in a back-bending mode. A plane S-shaped parallel connection way is adopted in space structures of two groups of the radio-frequency coils, and two groups of the radio-frequency coils are strictly symmetrical in space distribution so that the directions of radio frequency current of the same coil position are the same. The invention further discloses an inductive coupling plasma injection device provided with the inductive coupling plasma coil. According to the inductive coupling plasma coil and the injection device, on one hand, standing wave effect in the coil can be reduced and uniformity of plasma can be increased, and on the other hand, impedance matching can be well achieved, coupling effect of the plasma is increased, the probability of chip pollution caused by sputtering of a quartz window due to over-high voltage is lowered, the uniform high-density plasma of a large area can be generated in a reaction cavity of a large area, and therefore requirements of laboratory rooms and industry in the micro electronics field are met.

This invention discloses a surrounding routing structure of a TFT LCD array base plate including: a base plate and an array structure formed on it, a repairing line formed on the base plate, a grid insulation layer formed on the line, a surrounding public electrode routing formed on the grid insulation layer and overlapped with the repairing wire, in which, the surrounding public electrode routing is in a net structure with the repairing wire crossover region. This invention also discloses another TFT LCD array base plate surrounding routing structure and a manufacturing method for the structure.

The invention provides a method for manufacturing a MOS transistor, comprising: a. providing a semiconductor substrate, dummy gate stacks, spacers, and source-drain regions; b. forming a first interlayer dielectric layer whose height is less than that of the dummy gate The height of the stack; c. remove the part of the first interlayer dielectric layer located at both ends away from the dummy gate stack to form a first vacancy; d. fill the second interlayer dielectric layer in the first vacancy, which The top is located between the top of the first interlayer dielectric layer and the top of the gate stack; e. forming a third interlayer dielectric layer to cover the first interlayer dielectric layer and the second interlayer dielectric layer; f. forming a through hole exposing the first interlayer dielectric layer in the interlayer dielectric layer; g. removing the first interlayer dielectric layer through the through hole to form a second vacancy; h. forming a cap layer to fill the through hole hole. The invention effectively reduces the gate parasitic capacitance and improves device performance.

The embodiment of the invention discloses a display panel and a display device. In the display panel, the base substrate includes a device setting area, a first non-display area, a display area and a second non-display area, the first non-display area surrounds the device setting area, and the display area surrounds the first non-display area; formed on the substrate A plurality of data lines on the substrate; the first metal layer, the second metal layer and the third metal layer formed on the base substrate, each data line includes a first wiring part, and the first wiring part is located on the second metal layer layer; part of the data lines passing through the first non-display area also includes a first jumper, and each first jumper is located in the third metal layer; or, each first jumper is located in the first metal layer or, part of the first bridging portion is located in the third metal layer, and part of the first bridging portion is located in the first metal layer, the above-mentioned display panel can make each size larger on the premise of ensuring a higher screen ratio of the display panel The device is installed and used normally.

The invention relates to a manufacturing method of a semiconductor memory. The manufacturing method includes: forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending along a first direction and repeatedly arranged in a second direction; forming barriers on the semiconductor substrate on which the bit line structures are formed layer, the barrier layer covers the semiconductor substrate and a plurality of bit line structures; forms a layer of sacrificial material filling the grooves between the bit line structures; forms a hard mask pattern, and uses the hard mask pattern as a mask plate to sacrificially The material layer is etched to form a plurality of strip-shaped sacrificial spacers extending along the second direction; a first protective spacer is formed on the sidewall of the sacrificial spacer, and the first protective spacer and the bit line structure jointly define a Capacitive contact window; removing the sacrificial spacer, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap.