37results about How to "Reduce body effect" patented technology

Active control of body contacts in memory devices can provide variable substrate voltages during device operation. The body contacts can be used to adjust the body bias of switches in activated memory cells, while maintaining the body bias of switches in inactive memory cells. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line (“WL”) is activated.

An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.

In an embodiment, an improved charge pump circuit is provided to control a threshold voltage increase of a charge transmission transistor during a charge transfer period, and to prevent a latch-up generation during a charge non-transfer period. A charge transmission transistor transmits the voltage of a boosting node to a high voltage generation terminal in response to the voltage of a control node. In a bulk connection switch, during the charge transfer period the high voltage generation terminal is connected to the bulk of the charge transmission transistor and during the charge non-transfer period the bulk is connected to the low voltage, being lower than that of the voltage appearing at the boosting node of the charge transmission transistor or the high voltage generation terminal. Charge transmission efficiency and pumping operation reliability are improved, increasing the reliability of data access operations in a semiconductor memory device, for example.

Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region and a second region; forming first nanowires over the first region of the semiconductor substrate; forming second nanowires with a diameter smaller than a diameter of the first nanowires over the second region of the semiconductor substrate; forming a first gate layer around the first nanowires; and forming a second gate layer around the second nanowires.

The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a fine-grained ramp generator for a two-step single-slope analog-to-digital converter. The present invention solves the problem of integral non-linearity (INL) and differential non-linearity (INL) of the ramp generator due to changes in the common-mode level of the output buffer of the ramp generator during the establishment of the ramp generator by adopting a mode invariant to the common mode of the output buffer module 205. Linearity (DNL), spurious-free dynamic range (SFDR) and other performance degradation problems; and at the same time avoid the problem of using substrate-source short circuit to introduce substrate parasitic capacitance into the loop, which is helpful for improving the output signal of the ramp generator The linearity has a good effect; also by adopting a feed-forward transconductance path structure and a resistor-capacitor compensation structure, the purpose of pole-zero cancellation of the output buffer module 205 of the refinement ramp generator is realized, and the refinement is optimized. The linearity, loop stability and settling time of the ramp generator output buffer module 205 are quantized.

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