36results about How to "Reduce body effect" patented technology

A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

A tunable antenna system is provided for a wearable personal computing device, such as a smartwatch. The tunable antenna system includes at least two antennas configured for respective sets of frequency ranges. One or more radiating elements of the antennas are formed from portions of a metal bezel of the wearable personal computing device. For at least one of the antennas, an aperture tuner and an impedance tuner positioned within the metal bezel are provided, e.g., to tune between various communication bands. Non-conductive slits may be positioned within the metal bezel to provide isolation between the antennas. A ground plane of the antenna system may be formed by a metallic component of the wearable personal computing device. The antenna system can be insulated from a wearer's skin by a non-metallic back cover and optionally a glass back plate arranged to contact the wearer's skin or clothing during use.

An electronic circuit for ion sensor with the body effect reduction includes a bridge-type floating source circuit provided with an input terminal, an output terminal reflecting the change in the potential dependent on ion concentration, and an ion-sensitive field effect transistor (ISFET) wherein one terminal of the ISFET is coupled with the output terminal; a current mirror for providing a current to the bridge-type circuit; a third transistor for receiving the operating current provided by the current mirror, identical to the current provided to the ISFET; a differential amplifying circuit, wherein one input terminal of the amplifying circuit is input with a reference voltage, and the other input terminal is coupled with the output of the bridge-type readout circuit; and a third amplifier to generate a differential output voltage compensated for the body effect, temperature and time drift effects.

The invention, which belongs to the technical field of analog circuit, discloses a high-speed and high-linearity grid voltage bootstrap switching circuit. According to the invention, GN node signals generated by a fourth PMOS transistor, an eighth NMOS transistor and a seventh NMOS transistor are used for controlling the grid electrode of the fourth NMOS transistor; in addition, the same signal, namely a GN node signal, is used for controlling a substrate of a sampling switch tube, so that the substrate potential of the sampling switch tube is kept consistent with the grid potential during sampling, and thus the speed of the circuit is increased; the parasitic capacitance of the grid terminal of the sampling switch tube is reduced by reducing the number of the tubes connected with the gridterminal of the sampling switch tube; meanwhile, the bulk effect in the secondary effect of the MOS tube is reduced, the linearity of the sampling switch tube is ensured, and finally, the precisionof the sampling switch circuit is improved.

An active charge pump circuit may include a charge pump circuit, a control circuit, and a charge transfer circuit. The charge pump circuit may generate a charge pumping voltage in response to an active enable signal. The control circuit may generate a charge transfer control signal varying between a ground voltage and a boosted power supply voltage that is twice as much as a power supply voltage in response to the active enable signal. The charge transfer circuit may output the charge pumping voltage as an active voltage in response to the charge transfer control signal.

The present invention relates to the obesity-curative or obesity-preventive effect of a Polygonum cuspidatum butanol fraction and a Polygonum cuspidatum ethylacetate fraction, and more particularly, to a pharmaceutical composition and a functional food for treating obesity, the pharmaceutical composition and the functional food comprising a Polygonum cuspidatum butanol fraction (POCU-1b) and an ethylacetate fraction as active ingredients, wherein the Polygonum cuspidatum butanol fraction and the ethylacetate fraction inhibit effectively the activity of pancreatic lipase, an important enzyme involving in fat absorption in a living body, and have excellent inhibitory effect on fat absorption in the short term fat absorption-inhibitory animal experiments using lipid emulsions.

A voltage reference generation circuit includes a current supply circuit and a core circuit. The current supply circuit is arranged to provide a plurality of currents. The core circuit is coupled to the current supply circuit, and arranged to receive the currents and accordingly generate a voltage reference. The core circuit includes a first transistor, a second transistor and a third transistor, wherein the first transistor and the third transistor generate a first gate-to-source voltage and a third gate-to-source voltage, respectively, according to a first current of the received currents; the second transistor generates a second gate-to-source voltage according to a second current of the received currents; and the voltage reference is generated according to the first gate-to-source voltage, the second gate-to-source voltage and the third gate-to-source voltage.

In an embodiment, a charge pump circuit comprises a first pump stage, including a first sub-pump coupled to a first pre-charge MOSFET transistor, wherein the first sub-pump is used to pump down a gate of the first pre-charge MOSFET transistor to thereby increase the pre-charge efficiency of the first pre-charge MOSFET transistor. The higher efficiency the re-charge MOSFET is, the lower the gate level of pass transistor is. Thus, the charge sharing efficiency becomes better, and the body effect will be eliminated. The following pump stage is the same as the first pump stage. In addition, this embodiment is implemented by PMOSFET only; therefore, only single well is needed and then a small layout area can be achieved. Consequently, a high efficiency negative pump can be obtained.

This invention relates to a food supplement for reducing body odor; it is a mixture of edible carriers with chitin aqueous solution lyophilized powder, chitosan aqueous solution lyophilized powder, chitin powder, chitosan powder, or the composition of these ingredients, and it comes in the form of tablets or pills. The invention has an outstanding effect in reducing various types of body odors, including Koreans' unique body odor, such as Kimchi smell or garlic smell, westerners' unique body odor, such as cheese smell or butter smell, Arabs' unique body odor, such as mutton smell, armpit odor and body odor that is unique in the aged.

Active control of body contacts in memory devices can provide variable substrate voltages during device operation. The body contacts can be used to adjust the body bias of switches in activated memory cells, while maintaining the body bias of switches in inactive memory cells. This can reduce the body effect (i.e., variation of the threshold voltage due to a variation of the substrate or bulk voltage) and can therefore provide improved array device performance (e.g., reduced data corruption) while the word line (“WL”) is activated.

The invention belongs to the technical field of analog-to-digital conversion, and particularly relates to a fine quantization ramp generator for a two-step monoclinic analog-to-digital converter. According to the fine quantization ramp generator, an output buffer module 205 adopts a common-mode invariant mode, so that the problem that the performances such as integral nonlinearity (INL), differential nonlinearity (DNL) and spurious-free dynamic range (SFDR) of the slope generator become poor due to the change of the common-mode level of the output buffer of the slope generator in the establishing process is solved; meanwhile, the problem that substrate parasitic capacitance is introduced into a loop by adopting substrate source short circuit is avoided, and a good effect of improving the linearity of an output signal of the ramp generator is achieved; in addition, a feedforward transconductance path structure and a resistance-capacitance compensation structure are adopted, so that thepurpose of zero-pole cancellation of an operational amplifier of the output buffer module 205 of the fine-quantization ramp generator is achieved, and the linearity, the loop stability and the establishing stabilization time of the output buffer module 205 of the fine quantization ramp generator are optimized.

A charge pump device and an operating method thereof are proposed. The charge pump device is composed of a plurality of stages of charge transfer units and an output unit that are cascaded together. Each stage of the charge transfer units includes a first node for input, a second node for output, a first circuit and a first capacitor. The first node or the second node is biased at a bias provided for the first circuit. Thereby, the first capacitors of the odd-numbered stage and the even-numbered stage of charge transfer units can respectively receive two clock signals that are mutually opposite in phase for complementary switching operating. Collocated with the switching of the output unit, an output voltage with a high negative level can be generated.

A semiconductor device includes a first active region and a second active region arranged along a first direction in a substrate, an element isolation layer extending in a second direction in the substrate to isolate the first active region and the second active region, a first gate electrode extending in the first direction on the first active region, a second gate electrode extending in the first direction on the second active region, and an isolation impurity region containing impurities of a first conductivity type in the substrate and disposed below the element isolation layer, in which the isolation impurity region includes a first isolation region and a second isolation region spaced apart from each other in the second direction, and at least a part of the substrate interposed between the first gate electrode and the second gate electrode is interposed between the first isolation region and the second isolation region.