135results about How to "Offset error" patented technology

Method, system and non-transitory computer-readable medium for fail-safe performance of a lane centering system. An electrical power steering (EPS) system of a vehicle is monitored for a failure and operation of the lane centering system is switched to a differential braking controller to output differential braking commands to a differential breaking system upon determining that a failure of the EPS system has occurred, where the output braking commands direct the differential braking system to apply force a brake for a wheel of vehicle, such by the applied braking force the vehicle follows a desired path determined for a lane centering operation.

A device for fast transition from preamble synchronization of a received baseband signal to demodulation of the received baseband signal may include a baseband chip tracking loop to generate an offset tracking value to track any initial chip phase offset and Doppler-caused baseband chip frequency drift associated with the received baseband signal. The device may also include a numerical controlled oscillator to correct any Doppler-caused phase rotation associated with the received signal. The device may additionally include a preamble synchronization unit to detect a preamble of the received baseband signal, and to measure a chip phase offset and a baseband Doppler frequency shift associated with the received baseband signal. The chip phase offset may be used to set an initial chip phase offset value of the chip tracking loop so that the chip tracking loop starts with approximately a zero pull-in error. The baseband Doppler frequency shift may be used to set initial frequency offset values in the chip tracking loop and the numerical controlled oscillator so that both start with substantially near-zero offset errors for substantially immediate demodulation of the received signal. The device may further include an output device to output the data demodulated from the received baseband signal.

A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.

The invention relates to a clock duty ratio adjusting circuit. The clock duty ratio adjusting circuit comprises a pulse generator, an RS trigger, a duty ratio detector, an adjusting circuit and a D trigger. The pulse generator, the RS trigger and the adjusting circuit are successively connected. The pulse generator is connected to the S input end of the RS trigger; the output end of the RS trigger is connected respectively to the D trigger, the duty ratio detector and the input end of the adjusting circuit; the anti-phase output end of the D trigger is connected to the input end of the duty ratio detector; the output end of the duty ratio detector is connected to the input end of the adjusting circuit; the output end of the adjusting circuit is connected to the R input end of the RS trigger; inputted clock signals are accessed into the pulse generator and the D trigger. According to the invention, an RS trigger is adopted to integrate the edges of a clock. The paths of the duty ratio detector and the adjusting circuit are separate from their output path. The signal outputting path is rather simplified and features low shaking characteristics. The adoption of integrator negative feedback continuous time adjusting enables high accuracy.

A semiconductor device for control applied to a constant-voltage power supply device includes a digital-analog converter circuit which outputs a reference voltage corresponding to a value of a first register with taking an output voltage of a reference voltage source as a criterial reference voltage, and generates a control signal for driving a power semiconductor device based on an output voltage of an error amplifier which differentially amplifies a feedback voltage obtained by resistive-dividing on an output voltage of the constant-voltage power supply device and the reference voltage. An analog-digital converter circuit which converts the feedback voltage to a digital value with taking the output voltage of the constant-voltage power supply device as a reference voltage is provided, and based on the output, a value of a first register is corrected so as to offset an effect of an error in voltage dividing ratio of a voltage dividing resistor circuit.

The embodiment of the invention provides a lane line updating method, device, equipment and system and a readable storage medium. The method comprises the following steps: obtaining a plurality of original images obtained by shooting lane lines and positioning information of each shot original image; identifying lane line pixel points from each original image; according to the positioning information of a plurality of discrete points of the lane line to be updated in the map data and the positioning information of each shot original image, calculating an offset vector of each discrete point relative to a lane line pixel point in each original image, and obtaining an offset vector set associated with each discrete point; performing vector aggregation on the offset vectors in each offset vector set to obtain an aggregation vector associated with each discrete point; and updating the lane line to be updated according to the target offset point pointed by the aggregation vector associatedwith each discrete point. According to the method provided by the embodiment of the invention, errors caused by single offset are eliminated, the cost is low, the stability is high, and the occurrenceis high.

A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.

The analog demultiplexer (FIG. 6) includes an input amplifier (A₁), and output amplifiers (AMP₁-AMP_N). The output and inverting (−) input of amplifiers (AMP₁-AMP_N) are connected by a respective capacitor (C₁-C_N). Switches (S_1a, S_1b, etc.) connect the output of amplifier (A₁) to the inverting input of one of (AMP₁-AMP_N). Switches (S_2a, S_2b, etc.) connect the output of one of (AMP₁-AMP_N) to the non-inverting input of the amplifier A₁. Switches (S_2a, S_2b, etc.) and (S_1a, S_1b, etc.) open and close together in pairs. With feedback from the output of (AMP₁-AMP_N) through (A₁), the gain and any offset of (AMP₁-AMP_N) is divided down by the gain of (A₁). Amplifier (A₁) has capacitors (C_S1 and C_S2) connected to its inputs. Switch (S₅₀) connects the inverting input of amplifier (A₁) to its output, and switch (S₄₀) connects the non-inverting input of (A₁) to a voltage reference (V_REF) matching (V_REF) applied to (AMP₂). Switches (S₃₀) and (S₃₅) connect (C_S1) and (C_S2) to the demultiplexer input (2). In operation, switches (S₄₀, S₅₀, S₃₀ and S₃₅) are initially closed, while switches (S_2a, S_2b, etc.) are open to charge both capacitors (C_S1) and (C_S2) and the inputs and output of (A₁) to (V_REF). Switch (S₅₀) provides feedback to divide down gain errors and offset of (A₁). Switches (S₃₀, S₃₅, S₄₀ and S₅₀) are then open, while one of switches (S_2a, S_2b, etc.) is closed with one switch (S_1a, S_1b, etc) to drive one of the output voltages (V_OUT1-V_OUTN). With inputs and outputs of (A₁) and the connected (AMP₁-AMP_N) initially be at (V_REF), very little settling time is needed.

The invention relates to an MEMS pressure sensor and a preparation method thereof. The MEMS pressure sensor comprises a pressure sensitive film, at least four front-side voltage dependent resistors and at least four back-side voltage dependent resistors, the pressure sensitive film includes a front side and a back side, each front-side voltage dependent resistor is arranged at the front side of the pressure sensitive film, each back-side voltage dependent resistor is arranged at the back side of the pressure sensitive film, and the front-side voltage dependent resistors and the back-side voltage dependent resistors are electrically connected to form a Wheatstone bridge. The change direction of the resistance, along with the pressure, of the front-side voltage dependent resistor is opposite to that of the resistance, along with the pressure, of the back-side voltage dependent resistor at the corresponding position, so that errors caused by technical conditions and/or external factors of the voltage dependent resistors are offset, and the output stability and precision of the MEMS pressure sensor are improved.

The invention discloses a system for testing the diffraction efficiency of an acousto-optic tunable filter (AOTF). The system comprises a wavelength tunable laser, a neutral density filter, a diaphragm orifice, a beam splitting mirror, a two-dimensional electric turnplate and an energy meter. The wavelength tunable laser can generate laser beams with continuously adjustable wavelength, the laser beams after passing through the neutral density filter and the diaphragm orifice are split into two beams of lasers with fixed beam splitting ratio by the beam splitting mirror, and the energy of reflecting beams is used as reference energy; transmission beams enter the AOTF, the energy of diffracted light is received when radio-frequency drive is applied to the transmission beams, and energy with direct penetration is received when the drive is not applied to the transmission beams, thereby calculating the diffraction efficiency of the AOTF. Meanwhile, the measurement of an aperture angle can be realized by changing the angle of incident light through the two-dimensional electric turnplate. The device has the characteristics of simple principle and strong operability, can meet the requirement of testing the continuous wavelength of the AOTF and can also enhance the testing accuracy greatly by utilizing reference beams generated by the beam splitting mirror.

The invention discloses a motor. The motor comprises a rotatable reluctance rotor and a stator, wherein the reluctance rotor is in a closed loop shape extending in the circumferential direction of the motor; the stator comprises a plurality of stator sections arranged in the circumferential direction of the motor; the number of the stator sections is equal to or smaller than the number of stator sections connected to form the closed loop shape extending in the circumferential direction of the motor; one of the two adjacent stator sections comprises an outer winding excitation stator block located on the outer side of the reluctance rotor in the radial direction of the motor and an inner permanent magnet excitation stator block located on the inner side of the reluctance rotor in the radial direction of the motor; and the other of the two adjacent stator sections comprises an outer permanent magnet excitation stator block located on the outer side of the reluctance rotor in the radial direction of the motor and an inner winding excitation stator block located on the inner side of the reluctance rotor in the radial direction of the motor. The motor provided by an embodiment of the invention is simple and compact in structure, low in material cost, high in system efficiency, suitable for occasions of household appliances, electric vehicles, wind power generation and the like, and wide in application range.