32results about How to "Less jitter" patented technology

In various embodiments, the invention provides a clock generator and / or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-wave or sinusoidal.

A frequency synthesizer is provided having a fractional-N control circuit and method. The control circuit can operate as having a modulator that selectively applies any fractional ratio to a frequency divider within, for example, a feedback loop of a PLL. The modulator can be a delta-sigma modulator or any sequential state machine that can be implemented as the control circuit, and can select amongst a plurality of vector values. The vector values can be spaced relatively close to each other, and the incoming present vector values can each be added to a value chosen from the immediately preceding set of potential values. The selector circuit chooses from among the present set of vector values depending on whether the sum is nearest a target value. The sum nearest the target value is, therefore, selected as the present vector value, and the process is repeated in time for each vector value having a corresponding P value to form a pattern of P values sent to the divider of the PLL. The incoming frequency can therefore be synthesized based on the modulated P values used by the feedback divider to produce the appropriate fractional-N divide ratio for the synthesized frequency.

A serializer serializes N data (N>2) in N stages into a serial data stream. Each stage includes a logic section and a first inverter. The logic section receives i-th data (where i is less than or equal to N) of the N parallel data to output the i-th data or inverted i-th data in response to an active status or an inactive status of an j-th clock signal (where j is less than or equal to N) of the N clock signals. The first inverter receives the i-th data or the inverted i-th data from the logic section and inverts the i-th data or the inverted i-th data to output a first output signal. The output signal of the serializer may have reduced jitter even when the serializer operates in a high speed and a low power condition.

A serializer serializes N data (N>2) in N stages into a serial data stream. Each stage includes a logic section and a first inverter. The logic section receives i-th data (where i is less than or equal to N) of the N parallel data to output the i-th data or inverted i-th data in response to an active status or an inactive status of an j-th clock signal (where j is less than or equal to N) of the N clock signals. The first inverter receives the i-th data or the inverted i-th data from the logic section and inverts the i-th data or the inverted i-th data to output a first output signal. The output signal of the serializer may have reduced jitter even when the serializer operates in a high speed and a low power condition.

An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

An image processor includes a motion vector acquisition section for acquiring and outputting an image motion vector in pixel or a predetermined block unit from plural frames included in an input image signal; and a frame interpolation section for generating an interpolated frame by using the motion vector provided by the motion vector acquisition section and for combining the interpolated frame with a frame of the input image signal, thereby composing a signal of a new frame sequence. The motion vector acquisition section includes a first motion vector acquisition section acquiring a motion vector by matching process and a second motion vector acquisition section acquiring a motion vector based on a relative misalignment of a predetermined edge component between two temporally successive frames in a specific area of an input image signal's frame.

A method and apparatus for correcting for deterministic jitter in a sequential sampling timebase. The value of a fine analog delay is held at a substantially constant nominal rate during a duration of a counting of a digital clock. A time difference between a trigger at which a fine analog delay starts measuring time and the occurrence of a digital pulse of a stable clock used to count a coarse delay is measured. An input waveform is sampled at a sample time having a nominal delay time. After sampling, a desired compensation time is provided for the sample of the input waveform in accordance with combinations of three independent variables defining a calibration table. The waveform is reconstructed by shifting a delay time of a sampled value of the input waveform from its nominal delay time in accordance with a value defined by the calibration table.

A spread spectrum clock generation circuit and a controlling method thereof are disclosed, which provide clocks having less jitter and ideal spread spectrum and enable a reduction in circuit scale and in power consumption. To this end, a current control type modulator 19a is equipped with a current source Ia (current 4i). A charger unit CGa and a discharger unit DGa are designed such that currents i, 2i and 4i are allowed to flow, for example, by properly setting the sizes of transistors. Modulation cycles CIa to CIIIa are repeated and an output code is generated from a switching control circuit 20a according to each modulation cycle. A switching unit SSa is controlled according to the output code, thereby charging or discharging a capacitor element C1 with a charge / discharge current CDI corresponding to the output code. Hence, charge amounts and discharge amounts for all the modulation cycles CIa to CIIIa have the same value, i.e., 6i [A·clock].

There is provided a timing generator for generating a timing signal based on a given reference clock, having a delaying circuit section for outputting each pulse of the reference clock by delaying by a value of delay given per each of the pulse and a pulse selecting and outputting section for passing and outputting only pulses to be outputted as the timing signal among the pulses outputted out of the delaying circuit section.

An optical-pickup hologram element has six regions on an x-y plane, divided as follows: the first region with a first line (an x-axis) and a second line that connects points (−xa, 0) and (−xb, yb); the second region with the first and second lines and a third line connecting points (xa, 0) and (xb, yb); the third region with the first and third lines; the fourth region with the first line and a fourth line connecting the point (xa, 0) and a point (xb, −yb); the fifth region with the first and fourth lines and a fifth line connecting the point (−xa, 0) and a point (−xb, −yb); and the sixth region with the first and fifth lines (xa<xb and −xb<−xa). The second and fifth, and the other regions are given astigmatism at different angles to the second line.

There is provided a timing generator for generating a timing signal based on a given reference clock, having a delaying circuit section for outputting each pulse of the reference clock by delaying by a value of delay given per each of the pulse and a pulse selecting and outputting section for passing and outputting only pulses to be outputted as the timing signal among the pulses outputted out of the delaying circuit section.

A clock generating device includes: a DDS circuit that generates a periodic signal; and a comparator that compares an input signal and a reference signal and outputs a binary signal. The clock generating device includes a rate-of-change correcting unit that applies correction for increasing a rate of change at a crossing point with the reference signal to the periodic signal generated by the DDS circuit.

A PLL controller for controlling the tracking rate of a phase-locked loop (PLL), in particular, controlling coefficients to be input to a device such as a multiplier of the phase-locked loop. A PLL controller receives a phase error between a horizontal sync signal in a video signal and a reference signal. Then an error amount detector measures the phase error using the N thresholds to output a control signal indicating any of N+1 levels. A coefficient selector outputs one of the N+1 gains as a coefficient signal, the one gain corresponding to the level indicated by the control signal, so that the tracking rate of the phase-locked loop is controlled in response to the input video signal, and thus a high-quality video image with less jitter can be provided.

In an imaging apparatus which subjects signal electric charges of photodiodes of IT-CCD for interlaced scanning of 1080 effective scanning lines to vertical pixel addition to be read out as image signals, at least one of vertical transfer at the last horizontal period and horizontal transfer at half period in reading of pixels is stopped while fixing pairs of vertical pixels to be subjected to vertical pixel addition to be read out as image signals of progressive scanning of 540 effective scanning lines from the CCD and the read-out image signals of 540 effective scanning lines are subjected to scanning line conversion of 3 to 4 to be converted into image signals of progressive scanning of 720 effective scanning lines, the image signals of progressive scanning of 720 effective scanning lines being outputted.

An optical-pickup hologram element has six regions on an x-y plane, divided as follows: the first region with a first line (an x-axis) and a second line that connects points (−xa, 0) and (−xb, yb); the second region with the first and second lines and a third line connecting points (xa, 0) and (xb, yb); the third region with the first and third lines; the fourth region with the first line and a fourth line connecting the point (xa, 0) and a point (xb, −yb); the fifth region with the first and fourth lines and a fifth line connecting the point (−xa, 0) and a point (−xb, −yb); and the sixth region with the first and fifth lines (xa<xb and −xb<−xa). The second and fifth, and the other regions are given astigmatism at different angles to the second line.