125results about How to "Increase the number of digits" patented technology

A digital ultrasound beam former for ultrasound imaging, that can be configured by a control processor to process the signals from ultrasound transducer arrays with variable number of elements at variable sampling frequencies, where the lowest sampling frequency allows for the highest number of array elements. The maximal number of array elements is reduced in the inverse proportion to the sampling frequency. Parallel coupling of transmit/receive circuits for each element allow adaption of the receive Noise Figure and transmit drive capabilities to variations in the electrical impedance of the array elements.

When processing a signal having a sequence of discrete values, wherein there is a first frequency range, in which the signal has a high energy, and wherein there is a second frequency range, in which the signal has a low energy, the sequence of discrete values is first manipulated to obtain a sequence of manipulated values, so that at least one of the manipulated values is non-integer. Then the sequence of manipulated values is rounded to obtain a sequence of manipulated values. The rounding is formed to effect a spectral shaping of a generated rounding error so that a spectrally shaped rounding error has a higher energy in the first frequency range than in the second frequency range. By spectrally shaping the rounding error so that the rounding error does not have any energy either in the storage areas where there is no signal energy, an especially efficient coding is obtained particularly in connection with a lossless coding context.

The present invention provides an image display capable of performing high-precision multi-gradation display while avoiding problems of a subtle noise and increase in a drive frequency. Display signal data of one frame is constructed by a plurality of sub frames of, for example, four sub frames 1/4 to 4/4. The 1/4 frame is set as an address period of an analog signal, the 2/4 frame is set as an analog gradation display period, the 3/4 frame is set as an address period of a digital signal, and the 4/4 frame is set as a digital gradation light emission period. The image display is constructed in such a manner that, in the analog gradation display period, an OLED device in a pixel emits light of time according to an analog signal voltage stored in a storage capacitor in the pixel by an analog drive signal circuit and, in the digital gradation display period, a binary light emitting operation of light emission and non light emission is performed according to a digital signal voltage stored in the storage capacitor by a digital signal driving circuit.

A liquid crystal display is provided, which includes: a liquid crystal panel assembly including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines; a signal controller for processing image data, the signal controller including a dynamic capacitance capture (“DCC”) block for modifying image data assigned to the pixels by selectively performing DCC on the image data based on the difference between the image data of a current frame (“current data”) and the image data of a previous frame (“previous data”); a gate driver for sequentially applying a gate-on voltage to the gate lines of the liquid crystal panel assembly; and a data driver selecting data voltages among a plurality of gray voltages in response to the modified image data from the signal controller and applies the data voltages to the data lines of the liquid crystal panel assembly.

The invention provides a data verification method in a storage medium, comprising: organizing an ECC data matrix; encoding the data to generate a row check code and a column check code; when performing data operations on the ECC data matrix, using the row check code and column The check code checks the data. The present invention has stronger error correction capability than the single row check, can correct more byte errors, can increase the number of check data, allows more error bits in the storage medium, and can be well Correct these errors. The invention can better support MLC and 4LC type storage media, and achieve the purpose of prolonging the service life of the storage medium, improving the utilization rate of the storage medium and reducing the system cost.

A digital ultrasound beam former for ultrasound imaging, that can be configured by a control processor to process the signals from ultrasound transducer arrays with variable number of elements at variable sampling frequencies, where the lowest sampling frequency allows for the highest number of array elements. The maximal number of array elements is reduced in the inverse proportion to the sampling frequency. The beam former can be operated both in a RF-sampling mode and a quadrature mode. Parallel coupling of transmit/receive circuits for each element allow adaption of the receive Noise Figure and transmit drive capabilities to variations in the electrical impedance of the array elements.

The invention discloses a chaotic sequence generation method and a sequence generator for high-speed high-accuracy chaotic functions. An initial key circuit stores the initial value of a chaotic latch unit, a u value key circuit stores a sequence ui value; each cp chaotic function finishes one-time interactive operation: a bitwise conversion circuit outputs a bitwise XOR to the chaotic latch unit, the bitwise XOR is used to realize a subtraction operation N minus one and minus the absolute value of xi and so on; a shift data selector takes the ui as an address code of the data selector, the data is shifted with a plurality of bits toward right, then the subtraction is used to realize a multiplication that the ui is multiplied by the data; the subtraction result is stored into the chaotic latch unit at the rising edge of the cp, each cp generates a 160-bit chaotic output; the randomness is good due to the existence of an initial key and a u value key; the precision is far greater than that of the double type, the cycle of the cp can reach 90ns, the encryption of a 128-bit plaintext needs 1.7us; the invention can be realized by using FPGAs, GPLDs and ASICs and so on, and is used in the network security technical field, particularly in the wireless networks and the wireless sensor networks.

A controller adapts the read voltage thresholds of a memory unit in a non-volatile memory. In one embodiment, the controller determines, based on statistics for a memory unit of the non-volatile memory, an operating state of the memory unit from among a plurality of possible operating states and adapts at least one read voltage threshold for a memory cell in the memory unit based on the determined operating state.

The invention relates to a capacity control digital frequency adjusting circuit which belongs to the frequency adjusting technology in the electronic technology field. The invention comprises a capacitance charge-discharge circuit and a variable capacitance circuit. In the variable capacitance circuit, the switching on-off of the switch tube is controlled by the output signal of the counter and thus the total capacitance value of the charge-discharge capacitance; therefore, the dither output of frequency can be achieved, the frequency spectrum of the former higher harmonic is extended to a new frequency range which lowers the frequency spectrum amplitude and thus the electromagnetic interference of the switch power supply is reduced. Compared with flow control digital frequency adjusting circuit, the invention can achieve the dither function of frequency much better and lower the peak value of the switch frequency higher harmonic frequency spectrum and thus inhibit electromagnetic interference, besides, the chip area is reduced greatly, the production costs are reduced efficiently and thus the invention can be applied widely in the switch power supply chip field.

An information processing device such as a game machine is selectively connectable to different peripheral devices such as memory devices. The peripheral devices may be provided with characteristics for distinguishing one from another. The information processing device carries out operations based on the peripheral device connected thereto The information processing device may also access memories which store data having different data widths.

A non-volatile memory includes a plurality of blocks of physical memory, including a target block and at least one source block containing at least some valid data and some invalid data. Responsive to determining to perform garbage collection for the non-volatile memory, the controller transfers valid data from the at least one source block to the target block. The controller ends garbage collection on the at least one source block with at least some valid data present in the at least one source block and all interfaces of the target block closed at the boundary of independent layers. In at least some embodiments, the target block may be configured to store more bits per cell than the at least one source block.

To achieve a wireless communication apparatus capable of lowering power consumption for a digital signal processing of a transmitter in response to a transmission path condition.

A wireless communication system performs communication by digital transmission or analog transmission of a signal processed by a digital signal processing unit in a transmitting section on a transmission side toward a reception side through a line, wherein a transmission path condition of the line is measured on the reception side, the transmission path condition is transmitted to the transmission side using a reverse line with respect to the above described line, and a bit width for signal processing of digital signal processing units such as a modulating unit and a digital/analog converting unit is varied by a bit width selecting unit in response to the transmission path condition of the line notified by the reverse line on the transmission side.

Provided is a semiconductor chip to generate an identification key. The semiconductor chip may include a first inverter having a first logic threshold, a second inverter having a second logic threshold, and a first switch. The first switch may include a first terminal and a second terminal, and may short or open a connection between the first terminal and the second terminal according to an first input voltage value. An input terminal of the first inverter, an output terminal, and the first terminal of the first switch may be connected to a first node. An output terminal of the first inverter, an input terminal of the second inverter, and the second terminal of the first switch may be connected to a second node.