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Capacity controlled numerical frequency modulation circuit

A frequency modulation and circuit technology, applied in the field of electronics, can solve the problems of large chip area and increased system cost of flow control digital frequency modulation circuit

Inactive Publication Date: 2008-06-11
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In order to solve the technical problem that the chip area occupied by the flow control digital frequency modulation circuit is relatively large, resulting in an increase in the cost of the designed system, the present invention proposes a new type of digital frequency modulation circuit-capacity control digital frequency modulation circuit. Fine-tuning the charging and discharging capacitors in the entire circuit to modulate the frequency generated by the entire circuit, so as to realize frequency modulation and reduce the peak value of the spectrum at the high-order harmonic of the single-chip switching frequency, and suppress electromagnetic interference

Method used

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specific Embodiment approach 1

[0051] The capacitance-controlled digital frequency modulation circuit, as shown in Figure 6, includes a capacitor charging and discharging circuit, and the capacitor charging and discharging circuit is composed of an Imain current source, a PMOS differential input pair, an INV inverter, a current sink, and a COM hysteresis comparator constitute. The input terminal of the Imain current source is connected to the external power supply VDD, and its output terminal is connected to the sources of the PMOS transistor MP11 and the PMOS transistor MP12 of the PMOS differential input pair. The gate of the PMOS transistor MP11 is connected to the inverting output terminal of the INV inverter, and the gate of the PMOS transistor MP12 is connected to the non-inverting input terminal of the INV inverter and the comparison output terminal of the COM hysteresis comparator. Gates of the current sink NMOS transistor MN11 and NMOS transistor MN12 are interconnected, and their sources are groun...

specific Embodiment approach 2

[0052] Embodiment 1 In the scheme, the clock control signal CLKh input by the clock signal input terminal CLK of the N-bit COUNTER counter in the variable capacitance circuit can be provided by the oscillation frequency signal fc output by the entire capacity-controlled digital frequency modulation circuit, that is The comparison output terminal of the COM hysteresis comparator is connected to the clock signal input terminal CLK of the N-bit COUNTER counter, as shown in FIG. 7 .

specific Embodiment approach 3

[0053] As shown in Figure 8, on the technical solution shown in Figure 5, the counting bit N of the N-bit COUNTER counter in the variable capacitance circuit is limited to 4, and the number of fine-tuning capacitors Ci (0≤i≤N) is 4 , that is, there are four trimming capacitors C0, C1, C2 and C3, and the number of NMOS switch transistors Mi (0≤i≤N) is 4, that is, there are four NMOS switch transistors M0, M1, M2 and M3.

[0054] Similar, also can be on the technical scheme shown in Fig. 4, Fig. 6 and Fig. 7, limit the value of the count position N of the N-bit COUNTER counter in the variable capacitance circuit to be 4, fine-tune capacitance Ci (0≤i≤N ) is 4, that is, there are four trimming capacitors C0, C1, C2 and C3, and the number of NMOS switch tubes Mi (0≤i≤N) is 4, that is, there are four NMOS switches M0, M1, M2 and M3 Tube, thus designing different implementations.

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Abstract

The invention relates to a capacity control digital frequency adjusting circuit which belongs to the frequency adjusting technology in the electronic technology field. The invention comprises a capacitance charge-discharge circuit and a variable capacitance circuit. In the variable capacitance circuit, the switching on-off of the switch tube is controlled by the output signal of the counter and thus the total capacitance value of the charge-discharge capacitance; therefore, the dither output of frequency can be achieved, the frequency spectrum of the former higher harmonic is extended to a new frequency range which lowers the frequency spectrum amplitude and thus the electromagnetic interference of the switch power supply is reduced. Compared with flow control digital frequency adjusting circuit, the invention can achieve the dither function of frequency much better and lower the peak value of the switch frequency higher harmonic frequency spectrum and thus inhibit electromagnetic interference, besides, the chip area is reduced greatly, the production costs are reduced efficiently and thus the invention can be applied widely in the switch power supply chip field.

Description

technical field [0001] The invention belongs to the field of electronic technology, relates to switching power supply technology and electromagnetic interference technology in the field of communication, in particular to frequency modulation (jitter) technology. Background technique [0002] With the continuous increase of switching power supply frequency, the problem of electromagnetic interference (EMI: ElectroMagnetic Interference) is becoming more and more serious. How to reduce the EMI of switching power supply is a hot research issue in the field of switching power supply at present. Scholars have proposed filtering, frequency modulation techniques and other methods to reduce EMI. [0003] The filtering method is used to reduce EMI, which is realized by means of EMI filter and the like. The circuit structure of the EMI filter is shown in Figure 1 (where the L terminal is the positive pole of the power supply, the N terminal is the negative pole of the power supply, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02M1/12H02M1/14H03H11/04
Inventor 李泽宏邵志刚赖昌菁张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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