30results about How to "Increase effective capacitance" patented technology

Discussed is a touch screen panel including: a substrate; a first line electrode in a mesh pattern on the substrate; a plurality of first segment electrodes disposed on the first line electrode; a second line electrode in a mesh pattern on the substrate, and disconnected in an intersection area where the second line electrode is to intersect the first line electrode; a plurality of second segment electrodes disposed on the second line electrode; and a plurality of connection electrodes that connect the disconnected second line electrode in the intersection area, wherein the first and second line electrodes reduce resistance, and the first and second segment electrodes increase effective capacitance for sensing a touch to thereby reduce an RC-delay in the touch screen panel.

A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

The present invention provides a thin film balun capable of preventing a resonant frequency from being increased to a high frequency, and thus realizing a preferable passage characteristic. A thin film balun 1 includes: an unbalanced transmission line 2 having a first coil portion C1 and a second coil portion C2; and a balanced transmission line 3 having a third coil portion C3 and a fourth coil portion C4 which are magnetically coupled with the first coil portion C1 and the second coil portion C2, respectively. The first coil portion C1 is connected to an unbalanced terminal T0, and the second coil portion C2 is connected to a ground terminal G (ground potential) via a capacitor D (C component). The third coil portion C3 is connected to a balanced terminal T1 and the fourth coil portion C4 is connected to a second balanced terminal T2. The capacitor D is provided, in a plan view, in an area S1 between the outer end of the unbalanced terminal T0 and the outer end of the ground terminal G.

A pixel structure includes a pixel unit layer and a first metal wire layer. Each of control signal line and first and second scan signal lines in the first metal wire layer is connected to each pixel unit in a corresponding row. An insulating layer is disposed between each first metal patterned section in the first metal wire layer and a corresponding row of pixel units. A second metal wire layer includes initial signal lines and second metal patterned sections. Each initial signal line is connected to each pixel unit in a corresponding row. Each second metal patterned section overlaps with one of the first metal patterned sections to form a capacitor. Each connection signal line in a third metal wire layer connects the first scan signal line of a current row of pixel units to the second scan signal line of a next row of pixel units.

A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

Various embodiments of the present technology may comprise methods and apparatus for increased sensitivity of a capacitive proximity sensor. The method and apparatus may comprise additional external capacitors coupled in parallel with internal variable capacitors to increase the effective capacitance of a detection circuit allowing for a larger sensing element, and therefore a stronger sensing field, without increasing the applied voltage or the internal capacitance of the proximity sensor. In alternative embodiments, the methods and apparatus may be configured to operate as one of a transmission electrode and a reception electrode to increase the strength of the sensing field.

This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.

A thin film balun that can be made smaller and thinner while maintaining required balun characteristics is provided. A thin film balun 1 includes: an unbalanced transmission line UL including a first coil portion C1 and a second coil portion C2; a balanced transmission line BL including a third coil portion C3 and a fourth coil portion C4 that are positioned facing and magnetically coupled to the first coil portion C1 and the second coil portion C2 respectively; an unbalanced terminal UT connected to the first coil portion C1; a ground terminal G connected to the second coil portion C2 via a C component D; and an electrode D2 connected to the ground terminal G and facing a part of the second coil portion C2. The C component D is formed by the electrode D2 and the part D1 of the second coil portion C2.

An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.

A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and / or stability of the overall circuit.

The present application discloses a method for fabricating a semiconductor device with capacitors having a shared electrode. The method includes providing a substrate, forming a first trench in the substrate, doping sidewalls and a bottom surface of the first trench to form a bottom conductive structure, forming a first insulating layer on the bottom conductive structure and in the first trench, forming a shared conductive layer on the first insulating layer, forming a second insulating layer on the shared conductive layer, forming a top conductive layer on the second insulating layer, and forming a connection structure electrically connecting the bottom conductive structure and the top conductive layer. The bottom conductive structure, the first insulating layer, and the shared conductive layer together configure a first capacitor unit. The shared conductive layer, the second insulating layer, and the top conductive layer together configure a second capacitor unit.

A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

A photoelectric conversion device (10) includes a first conductivity type first semiconductor region (10a) located in a pixel region (11), a second conductivity type second semiconductor region (12) provided in the first semiconductor region (10a), for storing a signal charge, interconnecting portions (13 and 14) for connecting the second semiconductor region (12) with a circuit element provided outside the pixel region (11), and an organic film (16) which is provided above a portion located in the pixel region (11) in the interconnecting portions (13 and 14) through an insulating protective film (15) and held at a predetermined potential. The organic film (16) is made of a thermoplastic polyimide resin containing one of a conductive particle and a conductive fiber.

A unity gain buffer shared by a charge pump and an active loop filter in a phase-locked loop is disclosed. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump andthe active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

The invention discloses a plasma display panel and a front substrate thereof. The front substrate comprises a plurality of pairs of maintaining electrodes distributed on the lower surface of the front substrate, front medium layers covered on the maintaining electrodes and the lower surface of the front substrate, and protective layers covered on the lower surfaces of the front medium layers; each pair of the plurality of pairs of maintaining electrodes comprise public electrodes and scanning electrodes, the public electrode and the scanning electrodes all comprise bus electrodes and transparent electrodes, wherein each transparent electrode comprises a discharge transparent electrode, an extending transparent electrode which extends from the top of one of a plurality of first retaining walls on a rear substrate of the plasma display panel and is connected with each bus electrode, and a connecting transparent electrode connected with the discharge transparent electrode and the extending transparent electrode; and the bus electrodes are arranged on one of a plurality of second retaining walls on the rear substrate of the plasma display panel and a place corresponding to one of the second retaining walls.

The invention discloses a high-density low-parasitic capacitor, comprising a PMOS capacitor, a first capacitor, a second capacitor, a third capacitor and an MIM capacitor, wherein the PMOS capacitor is composed of a polysilicon gate, gate oxide, and a source electrode, a drain electrode and an N-well; the source electrode, the drain electrode and an N-well are connected together; the first capacitor is arranged between the polysilicon gate and the metal at the first layer; the second capacitor is arranged between metals at the same layer; the metal at the first layer is composed of a metal block array, and each metal block and an adjacent metal block thereof are respectively connected with the port A and port B of the second capacitor; the third capacitor is arranged between through holes, and each through hole and an adjacent through hole thereof are respectively connected with the port A and port B of the capacitor; and the MIM capacitor is provided an upper polar plate and a lower polar plate which are respectively connected to the port A and port B of the capacitor. In the invention, the capacitor between the polysilicon gate and the metal layer, the capacitor between the metals at the same layer, the capacitor between the through holes, the MIM capacitor and the like are realized on an MOS capacitor, thus reaching the maximal capacitance on a unit area.

The invention provides a MEMS microphone, comprising a base with an acoustic cavity, a back plate fixed to the base, and a vibrating membrane that is spaced apart from the back plate to form a capacitive structure, and the back plate includes a back plate and fixed electrodes; the vibrating membrane includes an effective vibrating part and an ineffective vibrating part, the effective vibrating part includes a vibrating body facing the acoustic cavity and a fixed arm extending from the vibrating body and fixed to the base, The vibrating body and the part of the fixed arm facing the acoustic cavity jointly form an effective vibration area; the ineffective vibration part is located between two adjacent fixed arms and is spaced apart from the effective vibration part, so The invalid vibration part is at least partially fixed on the base; the fixed electrode has the same shape as the effective vibration area. Compared with related technologies, the MEMS microphone of the invention has better acoustic performance.