121results about How to "High-density arrangement" patented technology

The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Disclosed is a display apparatus comprising an active matrix display section including a plurality of signal lines and scan lines, arranged in a matrix on a substrate, and a plurality of pixels and active elements arranged at intersections of the signal and scan lines, a scan line driving circuit for driving the scan lines and a signal line driving circuit for driving the signal lines. The display section has a non-rectangular shape. The active elements that make up the scan line driving circuit and / or the signal line driving circuit are formed by the same manufacturing process as that for forming the active elements in the active matrix display section. The scan line driving circuit and / or the signal line driving circuit are each a set of circuit units having the same function. These circuit units are arranged to conform to and extend around the outer circumference of the non-rectangular display section.

An input device having touched position detecting means for outputting a signal indicating a touched position during a period of time of touch when the touched position detecting means is touched, wherein a character and a symbol are inputted to be displayed on a display screen. Provided are: a virtual keyboard in which each virtual key corresponding to a plurality of characters or symbols is arranged corresponding to each divided area on the touched position detecting means; means for outputting, during the period of time of touch, a code signal indicating a character or a symbol of a virtual key corresponding to an area including the touched position; means for temporarily displaying on the display screen a character or a symbol of the outputted code signal; and means for determinately displaying the character or the symbol on the display screen when the code signal has disappeared.

A battery and a battery pack comprising a rechargeable battery (2) and a circuit substrate (3) integrated therein by a resin mold package (11) are provided. Resin is filled between the rechargeable battery (2) and the substrate (3) electrically connected thereto, so as to unite them as one battery or battery pack. The rechargeable battery (2) includes an engaging member (26) which functions as an anchor to the resin mold package (11) formed onto the battery, whereby the resin mold package (11) is firmly joined to the rechargeable battery (2). A thermo-sensitive element can be incorporated either on the circuit substrate (3) or within the space filled with resin.

A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.

The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

A phase change memory device comprises: a phase change element for rewritably storing data by changing a resistance state; a memory cell arranged at an intersection of a word line and a bit line and formed of the phase change element and a diode connected in series; a select transistor formed in a diffusion layer below the memory cell, for selectively controlling electric connection between an anode of the diode and a ground line in response to a potential of the word line connected to a gate; and a precharge circuit for precharging the diffusion layer below the memory cell corresponding to a non-selected word line to a predetermined voltage and for disconnecting the diffusion layer below the memory cell corresponding to a selected word line from the predetermined voltage.

The method of manufacturing a wiring substrate comprises the steps of: performing a pattern exposure of a resin layer containing photocatalyst particles, in a shape of a desired wiring pattern so that the photocatalyst particles are exposed at a surface of the resin layer; performing irradiation of radiation to the resin layer having the exposed photocatalyst particles while the resin layer having the exposed photocatalyst particles is immersed in an aqueous solution of a metallic salt so that a photochemical reduction and precipitating of a metal film onto the exposed photocatalyst particles are performed; and forming a conducting layer on the metal film.

A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line.

A terminal, adapted for electrically connecting an IC package and a printed circuit board, comprises: a base, a first elastic arm and a second elastic arm. The first elastic arm and the second elastic arm laterally and upwardly extend from a top and a bottom of the base, respectively. Each of the elastic arms has a contact tip on a free end thereof, and each of the two contact tips defines a gap to divide the contact tip into two contacting segments. After the terminal is punched from a metal piece, the gap is inwardly pressed on two sides thereof to have a narrow part between the contacting segments, so a width of the contact tip is reduce.

A connector assembly, for electrically connecting electrical cables 7 to a test head 4, comprises a plurality of types of cable side connectors 8 respectively attached to one end of the electrical cable 7; and a intermediate connector 6 to which the plurality of types of cable side connectors 8 are connected in a detachable manner, and the intermediate connector 6 having a first engagement part 501 having a shape with which all types of cable side connectors 8 can be engaged and an output terminal 602 able to be engaged with a test head side connector 41 electrically connected to a pin electronics board of the test head 4.

The present invention is directed to a socket connector (TS) having a plurality of contacts to be brought into contact with a plurality of solder balls (S) of a semiconductor package, a socket body (15) in which a mounting hole (11) is provided for each contact (10), a through-hole pierced in a height direction of the socket body and a contact support hole (13) are provided. Each contact (10) is provided with an upright piece (101) extending through the through-hole, a support piece extending from a proximal end side of the upright piece to be inserted into the through-hole and a contact portion (103) formed at a free end portion of the upright piece to be brought into contact with the solder ball. Each contact portion is arranged at a height level such that it projects from the surface of the socket body. A guide projection (14) is provided at a position to face an associated contact portion of each contact. These contact portion and guide projection are set at an interval such that the solder ball may be brought into contact with the both.

An optical connector to which an optical fiber cord including an optical fiber ribbon and a sheath is to be attached includes: a ferrule member a fusion splice protection sleeve, housing and a fixing member. The ferrule member holds a plurality of embedded fibers which are to be fusion-spliced respectively to a plurality of optical fibers constituting the optical fiber ribbon. The fusion splice protection sleeve protects a fusion-spliced portion. The housing houses the ferrule member and the fusion splice protection sleeve. The housing has, at the rear end, a recess for receiving a bifurcated portion of the sheath. The fixing member fixes the sheath to the housings and by holding it.

A connector assembly, for electrically connecting electrical cables 7 to a test head 4, comprises a plurality of types of cable side connectors 8 respectively attached to one end of the electrical cable 7; and a intermediate connector 6 to which the plurality of types of cable side connectors 8 are connected in a detachable manner, and the intermediate connector 6 having a first engagement part 501 having a shape with which all types of cable side connectors 8 can be engaged and an output terminal 602 able to be engaged with a test head side connector 41 electrically connected to a pin electronics board of the test head 4.

On the back surface of a transparent plate having a light extracting part 14 for outputting lights to the outside, an electrode 16 for wiring, and an electrode 17 for an electromagnetic shield, an optical device 11 is flip-chip mounted right under the light extracting part 14, an a driver IC 12 is flip-chip mounted at a desired position with metal bumps 15. When currents driving the optical device 11 flow from the driver IC 12 according to an electric logical signal from the outside, an optical signal is emitted from the optical device 11, and is output to the outside through the light extracting part 14. The light extracting part 14 may be provided with a light coupling material or an optical axis converter.

A field region forming a transistor is provided in a direction crossing a word line and a bit line. A bit line contact is provided corresponding to each bit line in a row direction. Storage node contacts are provided in alignment corresponding to respective columns in the row direction. The size of a basic cell region for forming a single memory cell can be set to 2·F·3·F. Here, F represents a minimum design size. Accordingly, memory cells in a twin cell mode DRAM storing one bit of data with two memory cells can be reduced in size.

Disclosed is a display apparatus comprising an active matrix display section including a plurality of signal lines and scan lines, arranged in a matrix on a substrate, and a plurality of pixels and active elements arranged at intersections of the signal and scan lines, a scan line driving circuit for driving the scan lines and a signal line driving circuit for driving the signal lines. The display section has a non-rectangular shape. The active elements that make up the scan line driving circuit and / or the signal line driving circuit are formed by the same manufacturing process as that for forming the active elements in the active matrix display section. The scan line driving circuit and / or the signal line driving circuit are each a set of circuit units having the same function. These circuit units are arranged to conform to and extend around the outer circumference of the non-rectangular display section.

The liquid ejection head for ejecting liquid from nozzles includes: pressure chambers connecting to the nozzles; a common liquid chamber which is connected to the pressure chambers, is arranged across the pressure chambers from the nozzles, and is defined by at least a multi-layer wiring substrate which has a recess-shaped structure including a base section forming one of a ceiling and a floor of the common liquid chamber and a projecting section forming a side wall of the common liquid chamber; electrical wires which are formed at least partially inside the multi-layer wiring substrate; and a connection electrode which is provided in a top of the projecting section of the multi-layer wiring substrate.

A semiconductor device comprises a package substrate, a semiconductor chip, a plurality of bump electrodes and one or more dummy chips. The semiconductor chip is mounted on one surface of the package substrate. The bump electrodes are the other surface of the package substrate and electrically connected to the semiconductor chip through a wiring structure. Each of the dummy chips is mounted on a predetermined region close to a corner portion of the semiconductor chip on the one surface of the package substrate.In the semiconductor chip, the dummy chips are formed of material having the same or similar coefficient of thermal expansion as that of the semiconductor chip. Therefore the stress caused by a difference between coefficients of thermal expansion is suppressed so as to improve connection reliability.

An electrooptical apparatus includes a light emission element array in which a plurality of light emission elements are arranged, and a barrier rib which surrounds the light emission element array.

A pattern forming method includes forming a resist film on a target film to be processed, which is formed on a substrate; and forming a basic pattern part in the resist film by multiple exposure using photomasks, wherein each exposure process is performed at an amount of exposure smaller than a threshold assigned to the resist film; and the resist film is developed after the total sum of the amounts of exposure through a plurality of exposure processes exceeds the threshold, so that the basic pattern part including a hole shape, which corresponds to each area where the total amount of exposure through the exposure processes via the photomasks exceeds the threshold, is formed in the resist film. The method also includes performing etching via the basic pattern part so as to form a desired pattern in the target film.

An ink-jet recording head has a plate-shaped member including a first layer with a partition wall formed by a first etching process and defining a pressure chamber, an ink inlet passage and a common ink storage chamber, a second layer with a land formed by a second etching process so as to correspond to the pressure chamber, and an intermediate layer sandwiched between the first and the second layers. The recording head also has a pressure producing device disposed with its extremity in contact with the land, and a nozzle plate with a nozzle hole bonded to the front surface of the plate-shaped member. An ink particle is jetted through the nozzle hole when the pressure in the pressure chamber is changed by the pressure producing device.

An inkjet head includes an actuator unit, and a flow path unit. Individual electrodes are formed on a piezoelectric sheet of the actuator unit. Pressure chambers are formed in a cavity plate of the flow path unit. Each individual electrode has a main electrode region disposed in a position opposite to a corresponding pressure chamber, and a land portion connected to the main electrode region. Overhang portions protruding in a direction along a surface of the cavity plate are formed in side walls of each pressure chamber. Each land portion at least partially overlaps a corresponding overhang portion at a height level (top height level) of a contact surface between the cavity plate and the actuator unit.

The liquid ejection head has nozzles for ejecting liquid in which a plurality of pressure chambers are arranged in a two-dimensional matrix configuration. The liquid ejection head comprises: pressure generating devices which are disposed so as to correspond to the pressure chambers and generate pressure for ejecting the liquid in the pressure chambers; pressure sensor members formed in at least two layers which determine the pressure inside the pressure chambers generated by the pressure generating devices; and electrodes which are disposed on both surfaces of one of the layers of the pressure sensor members and cause the one of the pressure sensor members to become effective determination sections.

To fabricate a semiconductor device, a pattern of recesses and lands is formed on a copper sheet as a matrix sheet, and BGA pads are formed on the lands on the copper sheet. An insulating layer is formed on the copper sheet to transfer the pattern of recesses and lands from the copper sheet to the insulating layer for thereby forming recesses in the insulating layer and placing BGA pads in the recesses in the insulating layer. Vias are formed through the insulating layer, and a conductive layer serving as circuits and interconnections is formed, the conductive layer being connected to the BGA pads by the vias. When the copper sheet is removed, the BGA pads are positioned within the recesses in the insulating layer. The BGA pads have surfaces positioned higher than the bottom of the recesses and lower than the surface of the insulating layer. A semiconductor chip is mounted on the conductive layer, and solder balls are joined to the BGA pads. Both the productivity of a process of mounting the solder balls and the bonding strength of the solder balls are increased.

A semiconductor device comprises a package substrate, a semiconductor chip, a plurality of bump electrodes and one or more dummy chips. The semiconductor chip is mounted on one surface of the package substrate. The bump electrodes are the other surface of the package substrate and electrically connected to the semiconductor chip through a wiring structure. Each of the dummy chips is mounted on a predetermined region close to a corner portion of the semiconductor chip on the one surface of the package substrate.In the semiconductor chip, the dummy chips are formed of material having the same or similar coefficient of thermal expansion as that of the semiconductor chip. Therefore the stress caused by a difference between coefficients of thermal expansion is suppressed so as to improve connection reliability.

The invention is a system and method for controllable alignment of any of a plurality of electro-optical components mounted to a circuit board with an optical axis. In one embodiment, the invention provides an improved illumination system for microscopy. The system incorporates a circuit board 31 providing structure and directly mounting a plurality of light emitting sources. The mounted light sources are rotatably alignable with a plurality of optical axes. The system further includes selectable conditioning of the sources.

A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line.

A liquid ejection head includes a passage member in which individual liquid passages are formed, diaphragms fixed to a plane of the passage member, piezoelectric layers formed on the diaphragms, individual electrodes formed on the respective piezoelectric layers, lands electrically connected to the respective individual electrodes. The lands have their height from a surface of the piezoelectric layers higher than that of the individual electrodes. Each of the individual liquid passages has a liquid ejection opening and a pressure chamber an interior space of which exposes on the plane. An overhang is formed on a side wall of each pressure chamber in such a manner that a length of an interior space of the pressure chamber along the plane increases at a portion more distant from the plane. At least a part of the land overlaps the overhang when seen in a direction perpendicular to the plane.