38results about How to "Avoid logic errors" patented technology

A logic process apparatus for composite graphs in a fixed layout document is provided in this invention. The apparatus includes a composite graph block extraction unit, for extracting composite graph blocks from the fixed layout document, a document parsing unit, for parsing the fixed layout document to obtain text primitives contained therein, a legend primitive extraction unit, for extracting legend primitives from the text primitives, a correlation detection unit, for detecting correlations between the composite graph blocks and the legend primitives, and a correlation storage unit, for storing the detected correlations. A logic process method for composite graphs in a fixed layout document is also provided.

The invention brings forward a switching operation bill generation method of a railway transformation and distribution substation. The method comprises the following steps: selecting an operation task and an operation mode, a system, through carrying out topology analysis on a main wiring diagram, listing circuit breakers of all outlet wires, upper and lower isolation knife brakes, buses, bus couplers and the like, then entering graphic billing, when switching operation is carried out and an operation bill is issued, first of all, selecting a current operation mode, secondly, selecting devices and cabinet bodies which are related to by operation of this time, according to the currently selected devices, extracting rules related with the operation from a rule base to establish a new rule table, for the new rule table, generating operation statements according to a first-transverse-and-then-longitudinal sequence, and filling a bill sample with the generated operation statements. According to the invention, a logic relation table with powerful functions can be automatically generated, through the table, the association sequence among operation cabinet bodies and the logic locking relations among operation devices can be solved, and operation bills of all operation types of a whole station can be automatically generated in an accurate manner.

The present invention discloses a method that can simultaneously support multiple sets of Cache data private segment dynamic settings, including step S1, determining n sets of private segment data location addresses that need to be set in the target data Cache, and setting corresponding n sets of private segment data for each private segment data. Cover the first private segment register; S2, respectively set the first comparator and the second comparator corresponding to each set of private segment data in the target data Cache; S3, perform the data row that needs to be written in the Cache according to certain rules Judging to determine whether it has "private segment standard"; S4, after confirming that it meets the "private segment standard", generate a private segment setting instruction in the instruction cache; S5, set the instruction emission rule judger to execute the instruction in the instruction cache The situation is judged; S6, after confirming that all the instructions arranged before the private section setting instruction in the instruction Cache have been executed, start to execute the private section setting instruction, and write the data row that needs to be written into the Cache into the corresponding private section location address In the associated data cache.

The invention discloses an implementing method and device of a Java integrated development environment. The implementing method and device are used for obtaining calling conditions of various variables in the Java integrated development environment to avoid logic errors in development. The method comprises the steps that current classes are traversed to obtain all methods and variables quoted in the current classes; by means of regularity of the Java language and rule matching, the classes where the methods and the variables are located are found out to be used as association classes of the current classes, and a correlation chart representing the calling relations of the current classes and all the association classes is obtained; all the classes in a current program are traversed, a main correlation chart of the calling relations of all the classes is obtained, and the main correlation chart is stored in the integrated development environment.

The invention relates to the field of data acquiring, in particular relates to a logic delay locking based anti-interference circuit and method, and aims at solving the problems in the prior art. The circuit and method are that a leading edge of a triggering signal is treated as a time reference point to lock an interference signal within a fixed delay range, so as to solve the interference problem related to a time sequence of the triggering signal. According to the circuit and method, a D triggering device is used for converting the triggering signal into a step signal which is synchronous with the leading edge; then a plurality of D triggering devices, a phase inverter and an NAND gate are used for converting the step signal into an inversion signal, wherein the leading time of the inversion signal is the same as that of the triggering signal, and the pulse width is determined by a clock cycle and the number of the D triggering devices; if the delay time of the interference relative to the triggering signal is less than the pulse width, the signal and the interference signal AND can be utilized to inhibit the interference signal within the pulse width.