Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

An anti-jamming circuit and method based on logic delay locking

A logic delay and delay circuit technology, applied in electrical components, pulse technology, pulse processing, etc., can solve problems such as time jitter, affecting the quality of trigger signals, and electronic devices cannot be accurately triggered, and achieve the purpose of suppressing signal interference signals. Effect

Inactive Publication Date: 2018-11-13
INST OF FLUID PHYSICS CHINA ACAD OF ENG PHYSICS
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Commonly used suppression measures such as shielding and filtering will always bring additional hardware costs, and may affect the quality of the trigger signal, especially the timing jitter, so that the electronic device cannot be accurately triggered

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • An anti-jamming circuit and method based on logic delay locking
  • An anti-jamming circuit and method based on logic delay locking

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] Example 1: as figure 1 shown. The circuit includes 4 D flip-flops (where D1 is used as a step signal generator, and the delay circuit includes flip-flop D2, flip-flop D3, and flip-flop D4), 2 inverters, 1 NAND gate and 1 AND gate . The trigger signal Trig1 is connected with the clock input of the flip-flop D1, the output of the flip-flop D1 is connected with the signal input of the flip-flop D2, the output of the flip-flop D2 is connected with the signal input of the flip-flop D3, and the output of the flip-flop D3 is connected with the flip-flop D4 The signal input ends are connected, and the clock signal 2MClk is connected with the clock input ends of the flip-flops D2 to D4 at the same time. The output of flip-flop D4 is connected to the input of inverter N1, the output of inverter N1 is connected to one input of NAND gate NA1, the output of flip-flop D1 is connected to the other input of NAND gate NA1, and the NAND The output end of the gate NA1 is connected with...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to the field of data acquiring, in particular relates to a logic delay locking based anti-interference circuit and method, and aims at solving the problems in the prior art. The circuit and method are that a leading edge of a triggering signal is treated as a time reference point to lock an interference signal within a fixed delay range, so as to solve the interference problem related to a time sequence of the triggering signal. According to the circuit and method, a D triggering device is used for converting the triggering signal into a step signal which is synchronous with the leading edge; then a plurality of D triggering devices, a phase inverter and an NAND gate are used for converting the step signal into an inversion signal, wherein the leading time of the inversion signal is the same as that of the triggering signal, and the pulse width is determined by a clock cycle and the number of the D triggering devices; if the delay time of the interference relative to the triggering signal is less than the pulse width, the signal and the interference signal AND can be utilized to inhibit the interference signal within the pulse width.

Description

technical field [0001] The invention relates to the field of data acquisition, in particular to an anti-interference circuit and method based on logic delay locking. Background technique [0002] In some physical experiments, the trigger signal used to trigger the electronic equipment is often accompanied by the interference signal. For example, when the high-power pulse device and the electronic equipment are simultaneously triggered by multiple synchronous trigger signals, the interference signal generated by the action of the high-power pulse device will affect the normal operation of the electronic equipment. The characteristics of these interference signals are that they follow the trigger and have a short duration (for example, less than 1 μS). After the high-power pulse device operates, some physical quantities need to be measured or processed, and the signals representing these physical quantities generally arrive after a certain delay time (eg, greater than 1.5 μS)...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/135
Inventor 叶超李洪涛谢敏李亚维龙燕
Owner INST OF FLUID PHYSICS CHINA ACAD OF ENG PHYSICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products