Low-power-consumption full adder circuit with reset function

Abstract

The invention discloses a low-power-consumption full adder circuit with a reset function, and belongs to the field of integrated circuits. Only ten transistors are adopted in the circuit, the circuitcomprises a reset circuit, two three-transistor XNOR circuits and a selection module circuit, and the reset circuit is composed of an NMOS transistor N6 and an NMOS transistor N7; the three-transistorXNOR circuit is composed of a PMOS transistor P1, an NMOS transistor N1 and an NMOS transistor N2 in a special connection mode. One selection module is composed of a PMOS tube P3 and an NOMS tube N5;the full adder circuit has the advantages that compared with a typical full adder circuit, the number of transistors is obviously reduced, power consumption is reduced, after a reset signal is introduced, the initial state of the full adder is conveniently determined, and an upper-layer circuit is more convenient to use.

Description

technical field [0001] The invention belongs to a full adder, in particular to a low-power full adder circuit with a reset function. Background technique [0002] The full adder is the basic unit of digital logic operations and is widely used in digital integrated circuit systems. With the development of modern electronic information technology, people have higher and higher requirements for the operation speed of integrated circuits, similar to the full adder The performance improvement of the basic unit becomes more and more important. For the full adder circuit, the internal transistor circuit design and the number of transistors have a huge impact on the performance of the full adder. Reducing the number of transistors can reduce the silicon area of ​​the chip, reduce delay and reduce power consumption. [0003] The early full adder has a large number of transistors, such as 40-tube complementary full adder, 28-tube resource multiplexing full adder and 24-tube mirror mu...

AI Technical Summary

Problems solved by technology

In the existing full adder, due to the large number of transistors and the large power consumption, the introduction of the reset circuit will increase the area of ​​the silicon chip, increase the power consumption, and reduce the speed, so the reset circuit is usually not introduced in the transistor level circuit.

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