A method that can simultaneously support multiple sets of cache data private segment dynamic settings

Abstract

The present invention discloses a method that can simultaneously support multiple sets of Cache data private segment dynamic settings, including step S1, determining n sets of private segment data location addresses that need to be set in the target data Cache, and setting corresponding n sets of private segment data for each private segment data. Cover the first private segment register; S2, respectively set the first comparator and the second comparator corresponding to each set of private segment data in the target data Cache; S3, perform the data row that needs to be written in the Cache according to certain rules Judging to determine whether it has "private segment standard"; S4, after confirming that it meets the "private segment standard", generate a private segment setting instruction in the instruction cache; S5, set the instruction emission rule judger to execute the instruction in the instruction cache The situation is judged; S6, after confirming that all the instructions arranged before the private section setting instruction in the instruction Cache have been executed, start to execute the private section setting instruction, and write the data row that needs to be written into the Cache into the corresponding private section location address In the associated data cache.

Description

technical field [0001] The invention relates to the field of computer storage systems, in particular to a method capable of supporting dynamic setting of multiple sets of Cache data private segments at the same time. Background technique [0002] During the development of computer technology, the access speed of the main memory has always been much slower than the processing speed of the CPU (processor), so that the high-speed processing capability of the CPU cannot be fully utilized, and the work efficiency of the entire computer system is affected. In order to alleviate the contradiction between the speed mismatch between the CPU and the main memory, a more commonly used method is to use a cache (high-speed cache) for caching at the storage level. [0003] At present, the cache size is one of the important indicators of the CPU, and its structure and size have a great impact on the CPU speed. Simply put, the cache is used to store some commonly used or soon-to-use data or...

AI Technical Summary

Problems solved by technology

However, there are some issues with the current private segment setup

First, the current private segment of the data cache is statically set. The private segment is set before the program starts running. It cannot be changed during the running of the program, and the changed private segment is not supported.

The second is that the current data cache settings generally only support a set of private segment settings. For discontinuous private segments, simultaneous support cannot be achieved.

[0005] In addition, after the existing data cache controllers dynamically set the private segment, most of them lack the judgment and execution capabilities of the stored instruction data pipeline for out-of-order emission and out-of-order execution, which will affect the setting of illegal private segments. Judgment result of the private segment of the Cache line

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