Method capable of simultaneously supporting dynamic setting of private segments of multiple sets of Cache data

Abstract

The invention discloses a method capable of simultaneously supporting dynamic setting of multiple sets of Cache data private segments, which comprises the following steps of: S1, determining n sets ofprivate segment data position addresses required to be set in a target data Cache, and setting n sets of corresponding first private segment registers for each set of private segment data; S2, respectively setting a first comparator and a second comparator corresponding to each set of private segment data in the target data Cache; s3, judging the data lines needing to be written into the Cache according to a certain rule to determine whether the data lines have a 'private segment standard 'or not; s4, generating a private segment setting instruction in the instruction Cache after confirming that the private segment standard is met; s5, setting an instruction transmitting rule judger, and judging an instruction execution condition in the instruction Cache; and S6, after it is confirmed that all the instructions arranged in front of the private segment setting instruction in the instruction Cache are executed, starting to execute the private segment setting instruction, and writing thedata line needing to be written into the Cache into the data Cache associated with the corresponding private segment position address.

Description

technical field [0001] The invention relates to the field of computer storage systems, in particular to a method capable of supporting dynamic setting of multiple sets of Cache data private segments at the same time. Background technique [0002] During the development of computer technology, the access speed of the main memory has always been much slower than the processing speed of the CPU (processor), so that the high-speed processing capability of the CPU cannot be fully utilized, and the work efficiency of the entire computer system is affected. In order to alleviate the contradiction between the speed mismatch between the CPU and the main memory, a more commonly used method is to use a cache (high-speed cache) for caching at the storage level. [0003] At present, the cache size is one of the important indicators of the CPU, and its structure and size have a great impact on the CPU speed. Simply put, the cache is used to store some commonly used or soon-to-use data or...

AI Technical Summary

Problems solved by technology

However, there are some issues with the current private segment setup

First, the current private segment of the data cache is statically set. The private segment is set before the program starts running. It cannot be changed during the running of the program, and the changed private segment is not supported.

The second is that the current data cache settings generally only support a set of private segment settings. For discontinuous private segments, simultaneous support cannot be achieved.

[0005] In addition, after the existing data cache controllers dynamically set the private segment, most of them lack the judgment and execution capabilities of the stored instruction data pipeline for out-of-order emission and out-of-order execution, which will affect the setting of illegal private segments. Judgment result of the private segment of the Cache line

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