Logic delay locking based anti-interference circuit and method
A logic delay and delay circuit technology, applied in the direction of single output arrangement, etc., can solve the problems of time jitter, affecting the quality of trigger signals, and electronic equipment cannot be accurately triggered, so as to achieve the effect of suppressing signal interference signals
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[0039] Embodiment 1: as figure 1 shown. The circuit includes 4 D flip-flops (where D1 is used as a step signal generator, and the delay circuit includes flip-flop D2, flip-flop D3, and flip-flop D4), 2 inverters, 1 NAND gate and 1 AND gate . The trigger signal Trig1 is connected to the clock input terminal of the trigger D1, the output terminal of the trigger D1 is connected to the signal input terminal of the trigger D2, the output terminal of the trigger D2 is connected to the signal input terminal of the trigger D3, and the output terminal of the trigger D3 is connected to the signal input terminal of the trigger D4 The signal input terminals are connected, and the clock signal 2MClk is connected with the clock input terminals of flip-flops D2-D4 at the same time. The output terminal of the trigger D4 is connected to the input terminal of the inverter N1, the output terminal of the inverter N1 is connected to one input terminal of the NAND gate NA1, the output terminal of...
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