35 results about "Threaded code" patented technology

A method for executing uniprocessor (UP) coded workloads in a computer capable of concurrent thread execution is disclosed. The method identifies threads in the uniprocessor coded workloads (UP-workloads) which can execute concurrently, and identifies threads in the UP-workloads which cannot execute concurrently. First threads which cannot execute concurrently are assigned to a first concurrency group. Second threads which cannot execute concurrently are assigned to a second concurrency group. Any thread in the first concurrency group can execute concurrently with any thread in the second concurrency group. The computer capable of concurrent thread execution then executes the UP-coded workloads in the first concurrency group at substantially the same time as executing the UP-coded workloads in the second concurrency group.

Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.

The present invention relates to a system and method for monitoring the operating state data of an industrial control graphical programming environment. The graphical program is built in the upper computer, and a memory allocation list is formed according to the storage structure of the graphical program. After compiling, the execution code and memory The allocation linked list is downloaded to the target machine; the target machine creates the main thread and the background thread, the main thread initializes the interpreter and executes the execution code periodically, and the background thread is responsible for interacting with the host computer; the host computer sends the data to the corresponding target machine according to the configuration information Dynamic monitoring command message; the target machine switches to the background thread to receive the dynamic monitoring command message after the end of the main thread code execution cycle, parses the command message, collects monitoring data and sends the data group package to the host computer , real-time dynamic refresh display. The invention realizes the real-time dynamic refreshing of monitoring data during the program running process, and the dynamic refreshing monitoring function does not affect the execution function of the control program.

An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and / or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.