35 results about "Threaded code" patented technology

A method for executing uniprocessor (UP) coded workloads in a computer capable of concurrent thread execution is disclosed. The method identifies threads in the uniprocessor coded workloads (UP-workloads) which can execute concurrently, and identifies threads in the UP-workloads which cannot execute concurrently. First threads which cannot execute concurrently are assigned to a first concurrency group. Second threads which cannot execute concurrently are assigned to a second concurrency group. Any thread in the first concurrency group can execute concurrently with any thread in the second concurrency group. The computer capable of concurrent thread execution then executes the UP-coded workloads in the first concurrency group at substantially the same time as executing the UP-coded workloads in the second concurrency group.

One embodiment of the present invention provides a system for communicating and performing synchronization operations between a main thread and a helper-thread. The system starts by executing a program in a main thread. Upon encountering a loop which has associated helper-thread code, the system commences the execution of the code by the helper-thread separately and in parallel with the main thread. While executing the code by the helper-thread, the system periodically checks the progress of the main thread and deactivates the helper-thread if the code being executed by the helper-thread is no longer performing useful work. Hence, the helper-thread is executes in advance of where the main thread is executing to prefetch data items for the main thread without unnecessarily consuming processor resources or hampering the execution of the main thread.

Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.

This disclosure describes a method and system that may enable fast, hardware-assisted, producer-consumer style communication of values between threads. The method, in one aspect, uses a dedicated hardware buffer as an intermediary storage for transferring values from registers in one thread to registers in another thread. The method may provide a generic, programmable solution that can transfer any subset of register values between threads in any given order, where the source and target registers may or may not be correlated. The method also may allow for determinate access times, since it completely bypasses the memory hierarchy. Also, the method is designed to be lightweight, focusing on communication, and keeping synchronization facilities orthogonal to the communication mechanism. It may be used by a helper thread that performs data prefetching for an application thread, for example, to initialize the upward-exposed reads in the address computation slice of the helper thread code.

The invention discloses a method, device, system and storage medium for realizing complex data analysis. In response to the data analysis instruction input by the user in the current WEB project, determine the corresponding current analysis function and the data to be processed, and search for the target interface corresponding to the current analysis function, and the target interface includes the data written in the data analysis software. The program code used to implement the current analysis function, calls the target interface, analyzes the data to be processed by the target interface, and obtains the data analysis result of the target interface. The program codes written in the software analyze complex data, and by using the powerful algorithm analysis capabilities of existing data analysis software, WEB projects developed in Java and other languages ​​can also have the function of dealing with complex algorithm problems, thereby avoiding manual processing in projects. Write multi-threaded code and other methods to deal with complex algorithm problems, which improves the efficiency of the program.

The present invention relates to a system and method for monitoring the operating state data of an industrial control graphical programming environment. The graphical program is built in the upper computer, and a memory allocation list is formed according to the storage structure of the graphical program. After compiling, the execution code and memory The allocation linked list is downloaded to the target machine; the target machine creates the main thread and the background thread, the main thread initializes the interpreter and executes the execution code periodically, and the background thread is responsible for interacting with the host computer; the host computer sends the data to the corresponding target machine according to the configuration information Dynamic monitoring command message; the target machine switches to the background thread to receive the dynamic monitoring command message after the end of the main thread code execution cycle, parses the command message, collects monitoring data and sends the data group package to the host computer , real-time dynamic refresh display. The invention realizes the real-time dynamic refreshing of monitoring data during the program running process, and the dynamic refreshing monitoring function does not affect the execution function of the control program.

An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and / or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.