48results about How to "Increase computing density" patented technology

A host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols.

The present invention discloses a render farm based on CPU cluster. A distributed parallel cluster rendering system is constructed with high-efficiency low-energy-consumption CPUs so that the computing power obtains and even exceeds the computing performance of a supercomputer. The invention settles a batch rendering problem in the digital innovation producing process. Through using the render farm based on the CPU cluster according to the invention, the producing of the three-dimensional cartoon, special effect of video image, architecture designing, etc. can be completed with a high efficiency. The render farm based on CPU cluster according to the invention further has the advantages of increasing the rendering speed for more than 40 times, reducing the investment cost of building the render farm for 20%-70%, and saving the energy consumption in the production process for 60%-80%.

A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

This relates to the manner in which computers are configured in a given area in order to conserve space and to deal with cooling issues associated with the close housing of a large number of computers. Efficient arrangements for efficiently increasing the density of computer configurations are shown, particularly when used in a network server or host environment.

This relates to the manner in which computers are configured in a given area in order to conserve space and to deal with cooling issues associated with the close housing of a large number of computers. Efficient arrangements for efficiently increasing the density of computer configurations are shown, particularly when used in a network server or host environment.

A radar system in which Coded Aperture Radar processing is performed on received radar signals reflected by one or more objects in a field of view which reflect a transmitted signal which covers a field of view with K sweeps and each sweep including Q frequency changes. For Type II CAR, the transmitted signal also includes N modulated codes per frequency step. The received radar signals are modulated by a plurality of binary modulators the results of which are applied to a mixer. The output of the mixer, for one acquisition results in a set of QK (for Type I CAR) or QKN (for Type II CAR) complex data samples, is distributed among a number of digital channels, each corresponding to a desired beam direction. For each channel, the complex digital samples are multiplied, sample by sample, by a complex signal mask that is different for each channel.

In order to realize computational programming, the invention provides an in-package lookup table-based programmable processor, comprising a logic chip and a programmable storage chip which are located in the same package; the programmable storage chip comprises a lookup table circuit (LUT), and the logic chip comprises an arithmetic logic circuit (ALC). According to a user need, the LUT stores relevant data of a needed function; the ALC performs arithmetic operation on the relevant data of the function.

The invention discloses a 1, 4-dinitro oxymethyl-3, 6-dinitro parazole [4, 3-c] pyrazole compound. The structure formula is shown in formula (I). The compound is used in the explosive field.

In order to realize computational programming, the invention provides a backside lookup table (BS-LUT)-based programmable processor, comprising a lookup table circuit (LUT) located on the backside of a processor substrate and an arithmetic logic circuit (ALC) located on the front of the processor substrate. According to a user need, the LUT stores relevant data of a needed function. The ALC performs arithmetic operation on the relevant data of the function.

A host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols.

The invention provides an in-package lookup table (IP-LUT)-based processor for calculating a mathematical function. The processor comprises a logic chip and a storage chip; the storage chip comprises a lookup table circuit (LUT), and data stored by the LUT is correlated to the mathematical function; the logic chip comprises an arithmetic logic circuit (ALC), and the ALC performs arithmetic operation on relevant data of the mathematical function; the storage chip and the logic chip are located in the same package.

The invention provides a backside lookup table (BS-LUT)-based emulation processor for emulating a system. The system comprises a subsystem. The emulation processor comprises a lookup table circuit (LUT) and an arithmetic logic circuit (ALC). The LUT is located on the backside of a processor substrate, and data stored by the LUT is correlated to a mathematical model of the subsystem. The ALC is located on the front of the processor substrate, and performs arithmetic operation on relevant data of the model. The LUT is electrically coupled with the ALC by multiple through silicon vias (TSV).

The invention provides a backside lookup table (BS-LUT)-based processor for calculating a mathematical function. The processor comprises a lookup table circuit (LUT) and an arithmetic logic circuit (ALC). The LUT is located on the backside of a processor substrate, and data stored by the LUT is correlated to the mathematical function. The ALC is located on the front of the processor substrate, and performs arithmetic operation on relevant data of the function. The LUT is electrically coupled with the ALC by multiple through silicon vias (TSV).

The invention provides an NAND operation circuit for memory area calculation, a memory chip and a computer. The NAND operation circuit for memory area calculation comprises a bit line pre-charging circuit, a storage array and a reverse-phase structure, which are connected in sequence; and the NAND operation circuit is located in a memory of the computer to ensure that the memory has a NAND operation function and then NAND operation of data can be completed in the memory, thereby avoiding the long-distance transmission, between the memory and an ALU, of the data needing NAND operation, improving the operation speed, in a CPU, of the data needing NAND operation, shorting a part of the data processing time of the CPU, namely, shortening the operation time of the CPU, improving the calculationdensity and calculation bandwidth, and realizing the operation by using a single memory process.

The invention provides an emulation processor for emulating a system. The to-be-emulated system comprises a subsystem. The emulation processor comprises a storage chip and a logic chip; the storage chip comprises a lookup table circuit (LUT), and data stored by the LUT is correlated to a mathematical model of the subsystem; the logic chip comprises an arithmetic logic circuit (ALC), and the ALC performs arithmetic operation on relevant data of the model; the storage chip and the logic chip are located in the same package.

The invention discloses a parallel navigation satellite signal tracking method based on GPU (graphics processing unit) and a system thereof. The method comprises the following steps: constructing a multichannel carrier tracking loop and a pseudo code tracking loop on CPU(central processing unit)-GPU, wherein the CPU is in charge of data reading, loop phase discrimination and control functions and the like, and the GPU is in charge of the relevant calculation and integral summation functions of a great quantity of data sequences; after the GPU finishes the integral summation calculation, adopting a two-stage binary tree calculation structure; calculating an error by a carrier phase discriminator and a CA (certification authority) code phase discriminator on the CPU; and controlling a local carrier phase and a CA code phase to correct to realize the tracking. According to the invention, the defects of poor flexibility and black box operation of a hardware receiver system and the defect that various navigation satellite signal systems can not be supported are overcome. Meanwhile, the processing speed and precision of a software receiver can be enhanced, the cost of the software receiver is lowered, and a GNSS (global navigation satellite system) software receiver can track the multichannel navigation satellite signal in real time.