47 results about "Ternary signal" patented technology

Disclosed is an optical transmitter module comprising: a precoder to generate an encoded binary signal from an electric signal; an amplifier to amplify the binary signal; a converter to convert the amplified encoded binary signal into a limited ternary signal; a frequency generator to generate a sine wave having a predetermined frequency; a multiplier to multiply the ternary signal using the sine wave; a light source to generate a coherent CW light having a constant intensity; and a Mach-Zehnder modulator to modulate the CW light according to the ternary signal from the multiplier.

In order to suppress occurrence of a random pattern signal is suppressed without the use of a sideband signal in a long distance data transmission exceeding that defined in a PCIe interface specification, provided is a computer system, including a first component having a transmitting unit which transmits a control signal, a second component having a receiving unit which receives the control signal, a transmission path which connects the first component and the second component along which a signal is transmitted and received, wherein: in case of the transmitting unit of the first component transmits a ternary signal with three states of 0/1/Idle to the receiving unit of the second component, the transmitting unit of the first component substitutes a combination of signals representing 0/1 for a signal representing the Idle state, and transmits the substituted signals instead of the ternary signal to the receiving unit of the second component.

Differential, current-steering DACs with reduced small signal differential non-linearity. A set of binary-weighted steerable constant current generators is used in which each constant current generator comprises a ternary constant current generator configured to generate a three-state differential current in response to a ternary signal on a control input. Each ternary current generator is associated with a bit of the binary code. The DAC further comprises a code converter coupled between a digital input, to receive a signed digital value for conversion, and control inputs of the steerable current generators, to convert the binary input code to a ternary code to control the steerable current generators to provide a differential analogue output. In embodiments the smallest current source is ½I₀ where I₀ is a change in differential output current caused by an 1sb change in the binary input code.

The invention discloses a ternary heat insulation D trigger and a four-bit ternary heat insulation synchronous reversible counter, wherein the ternary heat insulation D trigger realizes corresponding circuits by taking the three elements theory of the circuit as guidance, combining with the three elements theory of the circuit and utilizing an NMOS (N-mental-oxide-semiconductor) transistor and a cross storage type structure with different threshold values; and the four-bit ternary heat insulation synchronous reversible counter realizes processing of a ternary signal by introducing the energy recovery theory of the heat insulation circuit, being based on the design principal of the a synchronous counter, coordinately using the ternary heat insulation D trigger, a ternary heat insulation reverse circulation gate, a ternary heat insulation reverse circulation circuit with a borrow function and a ternary heat insulation one-out-of-two data selector, adopting a two-phase power clock and utilizing a bootstrapping operated MOS (metal-oxide semiconductor) pipe with different threshold values to finish injecting and recovering the energy output by the circuit. The ternary heat insulation D trigger and the four-bit ternary heat insulation synchronous reversible counter have the advantages that the connection lines between the circuits are reduced, the chip area is saved, the packaging intensity of the integrated circuit is increased, the circuit power consumption is effectively reduced, and the average power consumption can be reduced to 67.5% compared with the traditional CMOS (complementary metal-oxide-semiconductor) synchronous reversible counter.

A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.

Disclosed is a method and a system for performing N-ary modulation in which bit errors may be reduced against symbol error. A binary signal, a bit length thereof being n, is associated with N-ary signals arranged in first and second phase planes respectively for transmission, wherein N is not a number belonging to powers of 2 but is a number belonging to a series beginning from 12 and sequentially doubled, that is, any one of 12, 24, 48, 96, . . . , and wherein n is such that, if the bit length n is 7, 9, 11, 13, . . . , the number N is 12, 24, 48, 96, . . . , respectively, two out of the n bits are allocated for identifying four quadrants of the first phase plane, two out of the remaining (n−2) bits are allocated for identifying four quadrants of the second phase plane. The binary signal of three out of the n bits is converted into two digits of ternary signals (T1, T2). The ternary signals are mapped to the first and second phase planes with rotational symmetry of 90° or with axial symmetry.

The invention is concerned with the delay time locking loop circuit, it is higher logical control accuracy and faster response characteristic, and restrains the effect leading by the power fluctuation and the molestation from the transmission line. It is: inserts the independent double-loop (the signal phase locking loop and the signal cycle locking loop) sample loop structure in the signal path, uses the ternary signal sample method to process phase (the earlier or later logical judgment) sample/text and signal cycle (the narrow or width logic judgment) sample/text for the clock/data signal, changes the phase and space between the ternary sample points by the voltage controlling delay line if the judgment exists deviation, processes sample of the signal phase and cycle again until lock the signal phase and cycle finally.

A logical transmission system includes a driver configured to receive a source data and output a first voltage at a first node; a transmission line of a characteristic impedance configured to couple the first node to a second node; a three-point three-level slicer configured to receive a second voltage at the second node and output a first ternary signal, a second ternary signal, and a third ternary in accordance with a first reference voltage, a second reference voltage, a first clock, a second clock, and a third clock; and a CDR (clock-data recovery) unit configured to receive a reference clock, the first ternary signal, the second ternary signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage, the first clock, the second clock, and the third clock.

A carbon nanotube-based ternary comparator including a first decoder, a second decoder, and a comparison circuit. The comparison circuit includes: a first comparison unit for producing a greater-than-or-equal-to signal, and a second comparison unit for producing a less-than-or-equal-to signal. A first two-bit ternary signal is input into the signal input terminal of the first decoder. A first three-bit binary signal and a phase inverted signal of the first three-bit binary signal are output from a signal output terminal of the first decoder. A second two-bit ternary signal is input into the signal input terminal of the second decoder. A second three-bit binary signal and a phase inverted signal of the second three-bit binary signal are output from the signal output terminal of the second decoder.

Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.

The invention proposes an impact monitoring system using a digital random demodulation and split recovery algorithm, and the system comprises an impact monitoring front end, a sampling trigger module,a signal conversion module, a digital random sampler, a host computer and other modules, wherein the impact monitoring front end and the sampling trigger module realize the real-time monitoring of animpact signal, and record the required information for the processing at the next layer structure; the signal conversion module converts the received voltage analog signal into a ternary signal basedon the level change of its amplitude and inputs the ternary signal into the digital random sampler; the digital random sampler performs compressed sampling on the ternary signal by digital random demodulation; and the upper computer implements algorithm recovery that can process the sampled signals in parallel, and accurately inverts the original impact signal waveform at high speed.